이 특허를 인용한 특허 (62)

1. Leiphart,Shane P., Advanced barrier liner formation for vias.

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2. Kim Dae Young (Kyoungki-do KRX), Capacitor of a semiconductor device.

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3. Kim,Tae Sung, Conductive elements for thin film transistors used in a flat panel display.

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4. Sriram Tirunelveli S. ; Westerheim Ann C. ; Maziarz John J. ; Bolkhovsky Vladimir, Electromigration-resistant via structure.

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5. Leiphart, Shane P., Enhanced barrier liner formation for via.

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6. Leiphart, Shane P., Enhanced barrier liner formation for vias.

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7. Inoue, Yasunori; Okayama, Yoshio, Fabrication method of semiconductor device and abrasive liquid used therein.

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8. Watanabe Hiroyuki,JPX ; Mizuhara Hideki,JPX ; Saito Kimihide,JPX, Fabrication method of semiconductor device including insulation film with decomposed organic content.

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9. Adrian Ng Choon Seng,SGX, Formation of a metal via using a raised metal plug structure.

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10. Aaron Schoenfeld ; Rajesh Somasekharan, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.

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11. Schoenfeld, Aaron; Somasekharan, Rajesh, Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same.

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12. Jang Syun-Ming,TWX ; Yu Chen-Hua,TWX ; Chen Lung,TWX ; Wu Lin-June,TWX, Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein.

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13. Clampitt Darwin A., Interconnections for semiconductor circuits.

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14. Ishikawa, Akira; Yamaguchi, Tetsuji, Manufacturing method for a display device.

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15. Inoue, Yasunori; Mizuhara, Hideki, Manufacturing method of semiconductor device including an insulation film on a conductive layer.

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16. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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17. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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18. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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19. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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20. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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21. Asami, Yoshinobu; Takano, Tamae; Sakakura, Masayuki; Nomura, Ryoji; Yamazaki, Shunpei, Memory device and manufacturing method the same.

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22. Hirao Shuji (Osaka JPX) Okada Hideko (Osaka JPX) Yano Kousaku (Osaka JPX), Memory device with tungsten and aluminum interconnects.

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23. Kim Dae Young,KRX, Method for fabricating a semiconductor device having a capacitor.

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24. Sandhu Gurtej S. ; Iyer Ravi, Method of forming aluminum film.

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25. Matsunaga Noriaki,JPX ; Shibata Hideki,JPX ; Matsuno Tadashi,JPX ; Usui Takamasa, Method of forming semiconductor device having an improved buried electrode formed by selective CVD.

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26. Taniguchi Toshio,JPX, Method of making a multi-level interconnect having a refractory metal wire and a degassed oxidized, TiN barrier layer.

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27. Sandhu Gurtej S. ; Iyer Ravi, Method of making a void-free aluminum film.

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28. Sandhu, Gurtej S.; Iyer, Ravi, Method of making a void-free aluminum film.

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29. Sandhu, Gurtej S.; Iyer, Ravi, Method of making a void-free aluminum film.

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30. Lian,Jingyu; Lin,Chenting; Nagel,Nicolas; Wise,Michael, Multi-layer electrode and method of forming the same.

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31. Taguchi Mitsuru,JPX ; Maeda Keiichi,JPX ; Suzawa Hiroshi,JPX ; Kenmotsu Hidenori,JPX ; Hirayama Teruo,JPX, Multilayer interconnect structure for semiconductor device and method of manufacturing same.

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32. Yamamoto Hiroshi,JPX ; Ohta Tomohiro,JPX ; Takeyasu Nobuyuki,JPX, Multilevel interconnect method of manufacturing.

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33. Marty Michel,FRX ; Passemard Gerard,FRX ; Wyborn Graeme,FRX, Multiple layer interconnects with low stray lateral capacitance.

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34. Ota Noriyuki,JPX, Non-volatile semiconductor memory cell array.

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35. Fu Jianming ; Chen Fusen, Process for forming improved titanium-containing barrier layers.

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36. Fu Jianming ; Chen Fusen, Process for forming improved titanium-containing barrier layers.

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37. Trung T. Doan, Robust pressure aluminum fill process.

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38. Clampitt Darwin A., Semiconductor circuit interconnections and methods of making such interconnections.

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39. Ishikawa,Akira; Yamaguchi,Tetsuji, Semiconductor device.

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40. Kitada,Hideki; Shimizu,Noriyoshi; Ohtsuka,Nobuyuki; Ohba,Takayuki, Semiconductor device and a manufacturing method thereof.

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41. Watanabe, Hiroyuki; Mizuhara, Hideki; Tanimoto, Shinichi; Nishida, Atsuhiro; Yamaoka, Yoshikazu; Inoue, Yasunori, Semiconductor device and fabrication method thereof.

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42. Matsubara, Naoteru; Mizuhara, Hideki; Goto, Takashi, Semiconductor device comprising an interconnect structure with a modified low dielectric insulation layer.

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43. Inoue Yasunori,JPX ; Tsujimura Kazutoshi,JPX ; Tanimoto Shinichi,JPX ; Yamashita Yasuhiko,JPX ; Yoneda Kiyoshi,JPX ; Ibara Yoshikazu,JPX, Semiconductor device having cap-metal layer.

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44. Inoue Yasunori,JPX ; Mizuhara Hideki,JPX, Semiconductor device including an intrusion film layer.

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45. Mizuhara Hideki,JPX ; Watanabe Hiroyuki,JPX ; Kojima Noriaki,JPX, Semiconductor device including insulation film and fabrication method thereof.

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46. Mizuhara Hideki,JPX ; Watanabe Hiroyuki,JPX ; Matsubara Naoteru,JPX, Semiconductor device including insulation film and fabrication method thereof.

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47. Mizuhara, Hideki; Watanabe, Hiroyuki; Matsubara, Naoteru, Semiconductor device including insulation film and fabrication method thereof.

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48. Ohno Yoshikazu,JPX, Semiconductor device with short circuit prevention and method of manufacturing thereof.

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49. Edward O. Travis ; Sejal N. Chheda ; Bradley P. Smith ; Ruiqi Tian, Semiconductor device, a process for a semiconductor device, and a process for making a masking database.

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50. Harada Shigeru,JPX ; Kishibe Kenji,JPX ; Ihisa Akira,JPX ; Mochizuki Hiroshi,JPX ; Tanaka Eisuke,JPX, Semiconductor integrated circuit interconnection structures and method of making the interconnection structures.

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51. Kikuchi Katsumi,JPX ; Shimoto Tadanori,JPX ; Matsui Koji,JPX ; Shibuya Akinobu,JPX, Thin film capacitor formed in via.

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52. Lu Jiong-Ping ; Hsu Wei-Yung ; Hong Qi-Zhong, TiN+Al films and processes.

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53. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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54. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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55. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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56. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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57. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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58. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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59. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

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60. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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61. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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62. Lin,Mou Shiung, Top layers of metal for high performance IC's.

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