이 특허를 인용한 특허 (46)

1. Young,Steven P., Columnar architecture.

   상세보기
2. Young, Steven P., Columnar floorplan.

   상세보기
3. Young,Steven P., Columnar floorplan.

   상세보기
4. Vadi, Vasisht Mantra; Young, Steven P.; Ghia, Atul V.; Bekele, Adebabay M.; Menon, Suresh M., Differential clock tree in an integrated circuit.

   상세보기
5. Liang Mike, Flip chip bump distribution on die.

   상세보기
6. Rao Ramoji Karumuri ; Liang Mike, Flip-chip integrated circuit routing to I/O devices.

   상세보기
7. Rao, Ramoji Karumuri; Liang, Mike, Flip-chip integrated circuit routing to I/O devices.

   상세보기
8. Bauer,Trevor J.; Young,Steven P., Formation of columnar application specific circuitry using a columnar programmable logic device.

   상세보기
9. Kazuhisa Miyamoto JP; Ryo Yamagata JP; Takayuki Uda JP, Input-output circuit cell and semiconductor integrated circuit apparatus.

   상세보기
10. Miyamoto Kazuhisa,JPX ; Yamagata Ryo,JPX ; Uda Takayuki,JPX, Input-output circuit cell and semiconductor integrated circuit apparatus.

    상세보기
11. Miyamoto Kazuhisa,JPX ; Yamagata Ryo,JPX ; Uda Takayuki,JPX, Input-output circuit cell and semiconductor integrated circuit apparatus.

    상세보기
12. James Roxby, Philip B.; Downs, Daniel J., Integrated circuit having a routing element selectively operable to function as an antenna.

    상세보기
13. Graef Stefan ; Siguenza Oscar M., Low impact signal buffering in integrated circuits.

    상세보기
14. Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.

    상세보기
15. Liang Mike, Method for distributing connection pads on a semiconductor die.

    상세보기
16. Soboleski Alfred J. (Sunnyvale CA) Sakaguchi Yukio (Los Altos CA), Method for minimizing clock skew in integrated circuits and printed circuits.

    상세보기
17. Crafts, Harold S., Method of constructing an integrated circuit comprising an embedded macro.

    상세보기
18. Crafts Harold S., Method of constructing an integrated circuit utilizing multiple layers of interconnect.

    상세보기
19. Chen, Coming; Wu, Juan-Yuan; Lur, Water, Method of designing active region pattern with shift dummy pattern.

    상세보기
20. Shigyo, Naoyuki; Yamaguchi, Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.

    상세보기
21. Shigyo, Naoyuki; Yamaguchi, Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.

    상세보기
22. Shigyo,Naoyuki; Yamaguchi,Tetsuya, Method of designing wiring structure of semiconductor device and wiring structure designed accordingly.

    상세보기
23. Crafts, Harold S., Method of forming sea-of-cells array of transistors.

    상세보기
24. Ngai, Tony; Rahman, Arifur; Wortman, Curt, Placement, rebuffering and routing structure for PLD interface.

    상세보기
25. Jones Gareth James,GBX ; Work Gordon Stirling,GBX, Programmable logic array with a hierarchical routing resource.

    상세보기
26. Crafts Harold S., Sea-of-cells array of transistors.

    상세보기
27. Crafts, Harold S., Sea-of-cells array of transistors.

    상세보기
28. Crafts, Harold S., Sea-of-cells array of transistors.

    상세보기
29. Crafts,Harold S., Sea-of-cells array of transistors.

    상세보기
30. Crafts,Harold S., Sea-of-cells array of transistors.

    상세보기
31. Harold S. Crafts, Sea-of-cells array of transistors.

    상세보기
32. Choi, Won Jun; Baek, Hyo Jin, Semiconductor apparatus.

    상세보기
33. Shimomura Hiroshi,JPX, Semiconductor device evaluation pattern and evaluation method.

    상세보기
34. Owa, Kouji, Semiconductor integrated circuit and method of designing semiconductor integrated circuit.

    상세보기
35. Sonohara,Hideo, Semiconductor integrated circuit device and layout method of patterns for semiconductor integrated circuit device.

    상세보기
36. Nobuyuki Ikeda JP, Semiconductor integrated circuit device and method of laying out clock driver used in the semiconductor integrated circuit device.

    상세보기
37. Shibayama, Mari; Ohmura, Ryuji; Koda, Yukiyoshi; Sugiura, Kazushi, Semiconductor module.

    상세보기
38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.

    상세보기
45. Nelson, Donald W.; Borodovsky, Yan A.; Phillips, Mark C., Unidirectional metal on layer with ebeam.

    상세보기
46. Liu, Louis Chao-Chiuan; Chen, Chien-Wen, Utilization of MACRO power routing area for buffer insertion.

    상세보기
더보기