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Adaptive programming method for antifuse technology

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/177
  • H01H-037/76
출원번호 US-0940125 (1992-09-03)
발명자 / 주소
  • Parlour David B. (Pittsburgh PA) Goetting F. Erich (Cupertino CA) Trimberger Stephen M. (San Jose CA)
출원인 / 주소
  • Xilinx, Inc. (San Jose CA 02)
인용정보 피인용 횟수 : 58  인용 특허 : 0

초록

For antifuse programmable integrated circuit devices, in particular FPGA devices, the invention allows for alternative routing around antifuses which fail to program. The chip architecture includes wiring segments and antifuses which together allow for alternative routes around every antifuse in the

대표청구항

A method of programming an antifuse programmable logic device having interconnect wiring segments, and antifuses which programmably connect said wiring segments to each other, said method comprising the steps of: providing a design in machine readable form, said design comprising connections between

이 특허를 인용한 특허 (58)

  1. Vadi,Vasisht Mantra, Adjustable global tap voltage to improve memory cell yield.
  2. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Antifuse interconnect between two conducting layers of a printed circuit board.
  3. Nathan Richard J. (Morgan Hill CA) Lan James J. D. (Fremont CA) Chiang Steve S. (Saratoga CA), Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printe.
  4. Trimberger,Steven M.; Bapat,Shekhar; Wells,Robert W.; Patrie,Robert D.; Lai,Andrew W., Application-specific methods for testing molectronic or nanoscale devices.
  5. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Shepherd William H. ; Xie John Y. ; Jiang Hang, Ball grid array structure and method for packaging an integrated circuit chip.
  6. Eaton David D. ; Wong Richard J. ; Apland James M., Charge pumps of antifuse programming circuitry powered from high voltage compatibility terminal.
  7. El Ayat Khaled ; Chan King W. ; Speers Theodore M., Circuits for testing the function circuit modules in an integrated circuit.
  8. Wichowski, Robert; Hansen, Harold J.; Hawes, Kevin G., Compact FPGA-based digital motor controller.
  9. Trimberger Stephen M., Computer-implemented method of optimizing a time multiplexed programmable logic device.
  10. Hanrahan, Shaila; Lam, Peter Shing Fai, Data transfer on reconfigurable chip.
  11. Nathan Richard J. ; Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Osann ; Jr. Robert, Device-under-test card for a burn-in board.
  12. Kolze Paige A. ; Stolmeijer Andre ; Eaton David D., Field programmable gate array having internal logic transistors with two differentgate insulator thicknesses.
  13. Asayeh, Reza, High density antifuse based partitioned FPGA architecture.
  14. Wang, Cheng C., Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network.
  15. Wang, Cheng C., Integrated circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network.
  16. Wong, Dale, Interconnection network for a field programmable gate array.
  17. Wong, Dale, Interconnection network for a field programmable gate array.
  18. Liberkowski Janusz B. (5884 Macadam Ct. San Jose CA 95123), Lattice interconnect method and apparatus for manufacturing multi-chip modules.
  19. Bednar, Thomas R.; Dunn, Paul E.; Gould, Scott W.; Panner, Jeannie H.; Zuchowski, Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.
  20. Bednar, Thomas R.; Dunn, Paul E.; Gould, Scott W.; Panner, Jeannie H.; Zuchowski, Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.
  21. Bednar,Thomas R.; Dunn,Paul E.; Gould,Scott W.; Panner,Jeannie H.; Zuchowski,Paul S., Macro design techniques to accommodate chip level wiring and circuit placement across the macro.
  22. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F. ; Xie John Y., Method and structure to interconnect traces of two conductive layers in a printed circuit board.
  23. Mohan Sundararajarao ; Trimberger Stephen M., Method for configuring FPGA memory planes for virtual hardware computation.
  24. Tahoori, Mehdi Baradaran; Toutounchi, Shahin, Method for locating faults in a programmable logic device.
  25. Balzli, Jr., Robert M., Method for placement and routing of a circuit design.
  26. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Method for supporting one or more electronic components.
  27. Guilley, Sylvain; Danger, Jean-Luc, Method for testing cryptographic circuits, secured cryptographic circuit capable of being tested, and method for wiring such circuit.
  28. Roy Kaushik (West Lafayette IN) Nag Sudip K. (Pittsburgh PA), Method of segmenting an FPGA channel architecture for maximum routability and performance.
  29. Stephen M. Trimberger ; Richard A. Carberry ; Robert Anders Johnson ; Jennifer Wong, Method of time multiplexing a programmable logic device.
  30. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  31. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Method of time multiplexing a programmable logic device.
  32. Trimberger,Stephen M., Methods for using defective programmable logic devices by customizing designs based on recorded defects.
  33. Trimberger, Stephen M., Methods of enabling the use of a defective programmable device.
  34. Trimberger, Stephen M., Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams.
  35. Trimberger, Stephen M.; Ehteshami, Babak, Methods of using one of a plurality of configuration bitstreams for an integrated circuit.
  36. Wang, Cheng C., Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same.
  37. Wang, Cheng C., Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same.
  38. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Multilayer board having insulating isolation rings.
  39. Trimberger, Stephen M., Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein.
  40. Trimberger,Stephen M., Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein.
  41. Trimberger Stephen M., Optimizing and operating a time multiplexed programmable logic device.
  42. Chua Hua-Thye, Programmable application specific integrated circuit employing antifuses and methods therefor.
  43. Gamal Abbas El ; El-Avat Khaled A. ; Mohsen Amr, Programmable interconnect architecture.
  44. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  45. Agrawal Om P. (Los Altos CA) Wright Michael J. (Boulder CO), Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses.
  46. Nathan Richard J. ; Lan James J. D. ; Chiang Steve S., Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect.
  47. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Programmable/reprogrammable structure using fuses and antifuses.
  48. Eaton David D. ; Varshney Sudarshan ; Kolze Paige A., Protection of logic modules in a field programmable gate array during antifuse programming.
  49. Chan, Michael; Leventis, Paul; Lewis, David; Zaveri, Ketan; Yi, Hyun Mo; Lane, Chris, Redundancy structures and methods in a programmable logic device.
  50. Chan, Michael; Leventis, Paul; Lewis, David; Zaveri, Ketan; Yi, Hyun Mo; Lane, Chris, Redundancy structures and methods in a programmable logic device.
  51. Trimberger,Stephen M., Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof.
  52. Sundararajarao Mohan ; Stephen M. Trimberger, System and method of computation in a programmable logic device using virtual instructions.
  53. MacArthur James ; Lacey Timothy, Techniques and circuits for high yield improvements in programmable devices using redundant routing resources.
  54. Shepherd William H. ; Chiang Steve S. ; Xie John Y., Use of conductive particles in a nonconductive body as an integrated circuit antifuse.
  55. Trimberger,Stephen M., Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits.
  56. Trimberger, Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.
  57. Trimberger, Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.
  58. Trimberger,Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.
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