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A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between t

A first power FET has a source terminal, a gate terminal and a drain terminal and a load is connected in series with the source terminal of the power FET. A circuit configuration for triggering the first power FET includes a first input terminal. A first diode and a capacitor are connected between the first input terminal and the gate terminal of the first power FET. A second FET of the opposite channel type from that of the first power FET has a gate terminal and has drain and source terminals defining a drain-to-source path. A second diode is connected between the first diode and the capacitor and is connected through the drain-to-source path of the second FET to the drain terminal of the power FET. A resistor is connected between the gate and source terminals of the second FET. A controllable switch is connected to the gate terminal of the second FET. A second input terminal is connected to the controllable switch for receiving a voltage being lower than a supply voltage. A third depletion FET has a gate terminal connected to the controllable switch and has drain and source terminals defining a drain-to-source path connected between the gate terminal and the source terminal of the first power FET for discharging a gate-to-source capacitance of the first power FET.

대표청구항 ▼

In a circuit including a first power FET having a source terminal, a gate terminal and a drain terminal connected to a power supply, and a load connected in series with the source terminal of the first power FET, a circuit configuration for triggering the first power FET, comprising: a) a first inpu

In a circuit including a first power FET having a source terminal, a gate terminal and a drain terminal connected to a power supply, and a load connected in series with the source terminal of the first power FET, a circuit configuration for triggering the first power FET, comprising: a) a first input terminal; b) a first diode and a capacitor connected between said first input terminal and the gate terminal of the first power FET; c) a second FET being of the opposite channel type from that of the first power FET, having a gate terminal and having drain and source terminals defining a drain-to-source path; d) a second diode being connected between said first diode and said capacitor and being connected through the drain-to-source path of said second FET to the drain terminal of the first power FET; e) a first resistor connected between the gate and source terminals of said second FET; f) a controllable switch connected to the gate terminal of said second FET; g) a third FET having drain and source terminals defining a drain-to-source path connected between the gate terminal and the source terminal of the first power FET for discharging a gate-to-source capacitance of the first power FET; h) said third FET being a depletion FET; i) said third FET having a gate terminal connected to said controllable switch; and j) a second input terminal connected to said controllable switch for receiving a voltage capable of blocking said third FET when said controllable switch is turned on.