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Ball grid array with via interconnection 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H05K-007/02
  • H01L-023/28
출원번호 US-0047721 (1993-04-14)
발명자 / 주소
  • Marrs Robert C. (Scottsdale AZ) Hirakawa Tadashi (Osaka JPX)
출원인 / 주소
  • Amkor Electronics, Inc. (Paoli PA 02) Teijin Limited (Osaka JPX 03)
인용정보 피인용 횟수 : 392  인용 특허 : 0

초록 ▼

A ball grid array is formed by mounting and electrically connecting one or more electronic devices to a substrate in which vias are formed to interconnect electrically conductive traces formed in a surface of the substrate to solder ball pads formed at an opposite surface of the substrate. The vias

대표청구항 ▼

A packaged integrated circuit, comprising: a substrate having first and second opposed surfaces, electrically conductive first traces being formed on the first surface of the substrate; a series of electrically conductive pads extending across a portion of the substrate opposite the first surface of

이 특허를 인용한 특허 (392)

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  169. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
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  170. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
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  171. Charles W. C. Lin SG, Method of connecting a conductive trace to a semiconductor chip.
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  172. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip.
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  173. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using a metal base.
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  174. Lin,Charles W. C., Method of connecting a conductive trace to a semiconductor chip using conductive adhesive.
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  175. Chiang, Cheng-Lien; Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching.
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  176. Lin,Charles W. C.; Chiang,Cheng Lien, Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip.
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  177. Distefano Thomas H. ; Smith John W. ; Fjelstad Joseph ; Mitchell Craig S. ; Karavakis Konstantine, Method of encapsulating a semiconductor package.
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  178. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.
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  179. Brand, Joseph M., Method of fabricating an encapsulant lock feature in integrated circuit packaging.
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  180. Joseph M. Brand, Method of fabricating an encapsulant lock feature in integrated circuit packaging.
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  181. Jiang, Tongbi, Method of fabricating tape attachment chip-on-board assemblies.
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  182. Tongbi Jiang, Method of fabricating tape attachment chip-on-board assemblies.
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  183. Chou William T. ; Beilin Solomon I. ; Lee Michael Guang-Tzong ; Peters Michael G. ; Wang Wen-Chou Vincent, Method of fabrication of multiple-layer high density substrate.
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  184. Vasudivan, Sunappan; Lu, Chee Wai; Lok, Boon Keng, Method of forming a circuit board.
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  185. Glenn Thomas P., Method of forming an integrated circuit device package using a plastic tape as a base.
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  186. DiStefano Thomas H. ; Smith John W. ; Kovac Zlata ; Karavakis Konstantine, Method of forming compliant microelectronic mounting device.
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  187. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly.
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  188. Huemoeller, Ronald P.; Sheridan, Richard P., Method of making a chip carrier package using laser ablation.
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  189. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly.
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  190. Freyman Bruce J. ; Darveaux Robert F., Method of making a molded flex circuit ball grid array.
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  191. Lin, Charles W. C., Method of making a pillar in a laminated structure for a semiconductor chip assembly.
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  192. Charles W. C. Lin SG, Method of making a semiconductor chip assembly.
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  193. Lin, Charles W. C., Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive.
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  194. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a bumped metal pillar.
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  195. Lin,Charles W. C.; Chen,Cheng Chung, Method of making a semiconductor chip assembly with a bumped terminal and a filler.
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  196. Lin, Charles W. C.; Chen, Cheng-Chung, Method of making a semiconductor chip assembly with a bumped terminal, a filler and an insulative base.
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  197. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a carved bumped terminal.
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  198. Wang, Chia-Chung; Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace and a substrate.
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  199. Charles W. C. Lin SG, Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
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  200. Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
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  201. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a laterally aligned bumped terminal and filler.
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  202. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.
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  203. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.
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  204. Chiang,Cheng Lien; Lin,Charles W. C., Method of making a semiconductor chip assembly with an embedded metal particle.
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  205. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.
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  206. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.
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  207. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.
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  208. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.
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  211. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
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  212. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
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  213. Charles W. C. Lin SG, Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly.
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  214. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.
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  215. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.
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  216. Freyman Bruce J. ; Briar John ; Maxcy Jack C., Method of making grid array assembly.
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  219. Hashimoto Nobuaki,JPX, Method of mounting electronic parts.
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  222. Patrick O. Weber, Method of underfilling an integrated circuit chip.
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  223. Viscarra, Alberto F.; Shah, Jayna J.; Isom, Robert S.; Koontz, Christopher R., Methods and apparatus for antenna having dual polarized radiating elements with enhanced heat dissipation.
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  226. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
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  227. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.
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