이 특허를 인용한 특허 (85)

1. Farber, David A.; Lachman, Ronald D., Accessing data in a data processing system.

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2. Mahan, Justin Michael; Hutchins, Edward A.; Toksvig, Michael J. M., Address independent shader program loading.

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3. Stevens, Roy M., Apparatus and method for selectively allocating cache lines in a partitioned cache shared by multiprocessors.

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4. Cumming Peter,FRX ; Grisenthwaite Richard,GB6, Cache memory.

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5. Yanai Moshe ; Vishlitzky Natan ; Alterescu Bruno ; Castel Daniel, Cache memory with an allocable micro-cache.

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6. Sturges, Andrew Craig; May, David, Cache system.

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7. Sturges, Andrew Craig; May, David, Cache system.

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8. Sturges,Andrew C.; May,David, Cache system.

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9. Treynor Benjamin S., Cache system.

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10. Schafer Bruce W. ; Teeters Jeffrey W. ; Chweh Mark C. ; Lee David A. ; O'Connell Daniel P. ; Ramanathan Gowri, Caching apparatus and method for enhancing retrieval of data from an optical storage device.

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11. Farber, David A.; Lachman, Ronald D., Computer file system using content-dependent file identifiers.

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12. Cain, III, Harold Wade; Choi, Jong-Deok; Serrano, Mauricio Jose; Zhuang, Xiaotong, Computer implemented method and system for accurate, efficient and adaptive calling context profiling.

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13. Cain, III, Harold Wade; Choi, Jong-Deok; Serrano, Mauricio Jose; Zhuang, Xiaotong, Computer implemented method and system for accurate, efficient and adaptive calling context profiling.

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14. Kirk David Brian, Computer system with private and shared partitions in cache.

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15. Karandikar, Ashish; Agarwal, Pooja, Configurable SIMD engine with high, low and mixed precision modes.

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16. Karandikar, Ashish; Gadre, Shirish; Gruner, Frederick R.; Sijstermans, Franciscus W., Context switching on a video processor having a scalar execution unit and a vector execution unit.

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17. Farber, David A.; Lachman, Ronald D., Controlling access to data in a data processing system.

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18. Stairs, John; Kristoffersen, Esben Nyhuus; Hejlsberg, Thomas, Data caching policy in multiple tenant enterprise resource planning system.

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19. Farber David A. ; Lachman Ronald D., Data processing system using substantially unique identifiers to identify data items, whereby identical data items hav.

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20. Rodriguez, Jorge R., Designing a cache using an LRU-LFU array.

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21. Rodriguez, Jorge R., Designing a cache with adaptive reconfiguration.

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22. Haines, Jonathan Williams; Cook, Brett Alan, Distributed media cache for data storage systems.

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23. Cherabuddi, Rajasekhar, Dynamically allocated cache memory for a multi-processor unit.

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24. Farber, David A.; Lachman, Ronald D., Enforcement and policing of licensed content using content-based identifiers.

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25. Rose, Anthony, Filter for a distributed network.

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26. Rose, Anthony, Filter for a distributed network.

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27. Rose, Anthony, Filter for a distributed network.

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28. Arimilli Ravi Kumar ; Clark Leo James ; Dodson John Steven ; Lewis Jerry Don, Hardware-managed programmable congruence class caching mechanism.

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29. Loafman,Zachary Merlynn, Increasing memory locality of filesystem synchronization operations.

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30. Crow, Franklin C.; Sewall, Jeffrey R., Interrupt handling techniques in the rasterizer of a GPU.

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31. Crow, Franklin C.; Sewall, Jeffrey R., Interrupt handling techniques in the rasterizer of a GPU.

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32. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D., Latency tolerant system for executing video processing operations.

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33. John W. Goetz ; Paul T. Gutwin ; Stephen W. Mahin ; Wilbur D. Pricer, Method and apparatus for improving caching within a processor system.

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34. Mackenthun, Donald W.; Bauman, Mitchell A.; Englin, Donald C., Method and apparatus for parallel store-in second level caching.

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35. Andersen, Erik, Method and apparatus for segmenting memory based upon bandwidth of a data communication platform.

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36. Andersen,Erik, Method and apparatus for segmenting memory based upon bandwidth of a data communication platform.

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37. Bullard, Justin; Opferman, Toby; Kasik, David J., Method and apparatus for updating a graphical display in a distributed processing environment.

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38. Bullard, Justin; Opferman, Toby, Method and apparatus for updating a graphical display in a distributed processing environment using compression.

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39. Bullard, Justin; Opferman, Toby, Method and apparatus for updating a graphical display in a distributed processing environment using compression.

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40. Wagar Bruce Alan (Los Banos CA) Gellai Andrew Paul (San Jose CA) Mead Janice K. (Cupertino CA), Method and system for dynamic performance resource management within a computer based system.

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41. Matthias Augustin Blumrich, Method and system for dynamically partitioning a shared cache.

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42. Collins, Henry, Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism.

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43. Collins, Henry, Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism.

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44. Collins,Henry, Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism.

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45. Collins,Henry, Method and system for efficiently reducing graphical display data for transmission over a low bandwidth transport protocol mechanism.

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46. Danskin, John M.; Tamasi, Anthony Michael, Method and system for implementing fragment operation processing across a graphics bus interconnect.

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47. Bowen, Andrew D., Method and system for non stalling pipeline instruction fetching from memory.

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48. Krantz Jeffrey Isaac ; Bloomfield Marc Alan ; Luu Thanh, Method for dynamically and efficiently caching objects by subdividing cache memory blocks into equally-sized sub-blocks.

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49. Krantz Jeffrey Isaac ; Bloomfield Marc Alan ; Luu Thanh, Method for dynamically and efficiently caching objects received from an application server by a client computer by subdividing cache memory blocks into equally-sized sub-blocks.

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50. Bloomfield Marc Alan ; Krantz Jeffrey Isaac, Method for lossless bandwidth compression of a series of glyphs.

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51. Hottgenroth, Dirk, Method for operating an integrated memory unit partitioned by an external control signal.

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52. Bloomfield Marc A., Method for the lossless compression of lines in a distributed computer system.

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53. Mackenthun Donald W. ; Bauman Mitchell A. ; Englin Donald C., Method of and apparatus for store-in second level cache flush.

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54. Anderson David P. ; Moorer James A., Method of dynamically allocating network node memory's partitions for caching distributed files.

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55. Karandikar, Ashish; Gadre, Shirish; Salek, Amir H., Methods and systems for command acceleration in a video processor via translation of scalar instructions into vector instructions.

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56. Steven D. Krueger ; Jonathan H. Shiell ; Ian Chen, Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure.

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57. Lew, Stephen D.; Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W., Multi context execution on a video processor.

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58. Karandikar, Ashish; Gadre, Shirish; Lew, Stephen D.; Cheng, Christopher T., Multidimensional datapath processing in a video processor.

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59. Garg, Atul; Sharma, Anil, Multistandard hardware video encoder.

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60. Kanuri, Mrudula, Optimal use of buffer space by a storage controller which writes retrieved data directly to a memory.

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61. Kumar Rajendra ; Emerson Paul Gene, Partitioned single array cache memory having first and second storage regions for storing non-branch and branch instruc.

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62. Dean, Alvar A.; Goodnow, Kenneth J.; Mahin, Stephen W.; Pricer, Wilbur D.; Thygesen, Dana J.; Ventrone, Sebastian T., Performance based system and method for dynamic allocation of a unified multiport cache.

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63. Karandikar, Ashish; Gadre, Shirish; Sijstermans, Franciscus W.; Su, Zhiqiang Jonathan, Pipelined L2 cache for memory transfers for a video processor.

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64. Vamanan, Balajee; Methar, Tukaram; Kanuri, Mrudula; Krishnan, Sreenivas, Processing of read requests in a memory controller using pre-fetch mechanism.

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65. Mahan, Justin Michael; Hutchins, Edward A.; Kubalska, Ewa M.; Battle, James T., Program sequencer for generating indeterminant length shader programs for a graphics processor.

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66. Lew, Stephen D.; Gadre, Shirish; Karandikar, Ashish; Sijstermans, Franciscus W., Programmable DMA engine for implementing memory transfers and video processing for a video processor.

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67. Wester,Rogier; Van De Waerdt,Jan Willem; Slavenburg,Gert, Reducing cache effects of certain code pieces.

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68. Coleman,Paul; Yang,Ruiguo; Collins,Henry, Reducing the amount of graphical line data transmitted via a low bandwidth transport protocol mechanism.

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69. Yang,Ruiguo; Collins,Henry, Remote control of a client's off-screen surface.

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70. Garg, Atul; Venkatapuram, Prahlad, Rewind-enabled hardware encoder.

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71. Lambright, Daniel; Ofer, Adi; Vishlitzky, Natan; Ofek, Yuval, Segmenting cache to provide varying service levels.

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72. Mahan, Justin Michael; Hutchins, Edward A., Shader program instruction fetch.

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73. Mahan, Justin Michael; Hutchins, Edward A., Software assisted shader merging.

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74. Arimilli Ravi Kumar ; Clark Leo James ; Dodson John Steven ; Lewis Jerry Don, Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels.

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75. Arimilli Ravi Kumar ; Clark Leo James ; Dodson John Steven ; Lewis Jerry Don, Software-managed programmable unified/split caching mechanism for instructions and data.

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76. Su, Zhiqiang Jonathan; Karandikar, Ashish, State machine control for a pipelined L2 cache to implement memory transfers for a video processor.

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77. Kultursay, Emre; Ebcioglu, Kemal; Kandemir, Mahmut Taylan, Storage unsharing.

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78. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D., Stream processing in a video processor.

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79. Jost Larry T., System for automatically and continuously tuning tunable parameters by setting tuning mechanism to tune a next tunable.

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80. Anemojanis Eugene, System for identifying memory segment bounded by previously accessed memory locations within data block and transferring.

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81. Hasenplaugh, William; Emer, Joel; Fossum, Tryggve; Jaleel, Aamer; Steely, Simon, Technique for controlling computing resources.

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82. Ju Seok-mann,KRX ; Huh Hyun-gue,KRX, Test method of cache memory of multiprocessor system.

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83. Luu, Viet-Tam; Pflughaupt, Russell, Validating a graphics pipeline using pre-determined schedules.

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84. Hewitt Larry, Vertical wavetable cache architecture in which the number of queues is substantially smaller than the total number of v.

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85. Gadre, Shirish; Karandikar, Ashish; Lew, Stephen D.; Cheng, Christopher T., Video processor having scalar and vector components.

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