[특허]Pyramid processor integrated circuit

Pyramid processor integrated circuit 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06K-009/36
출원번호	US-0805149 (1991-12-11)
발명자 / 주소	van der Wal Gooitzen S. (Lawrenceville NJ)
출원인 / 주소	David Sarnoff Research Center, Inc. (Princeton NJ 02)
인용정보	피인용 횟수 : 31 인용 특허 : 0

초록 ▼

Multiresolution (pyramid) filtering is useful in image processing. An IC for implementing a variety of multiresolution filters includes a programmable, symmetric, and separable two-dimensional filter. The input signal to the filter can be an input signal applied to the IC or a combination of two such signals. Circuitry in the IC may be programmed to imply pixel values around the edges of the two-dimensional image signals processed by the filter. The filter provides an output signal as well as each of the unfiltered signals from a tapped delay line of a filter that combines successive lines of the image. The IC also includes an arithmetic and logic unit in which the filtered output signal may be combined with an unfiltered input signal or one of the unfiltered tap signals. If the filter is programmed to produce a Gaussian low-pass filtered image, this image, combined with image data from a center one of the filter taps produces a Laplacian function of the original image.

대표청구항 ▼

A pyramid processor comprising: means for receiving a first and a second digital data input signal, each including a data signal component and a timing signal component; first means, responsive to a first control signal, for selectively combining the respective data signal components of the first and second digital data signals to generate a third digital data signal, and for delaying and selectively combining the respective timing signal components of the first and second digital data signals to compensate for delays incurred in processing the first and second data signals and for combining the compensated timing signal with the third digital data signal; two-dimensional digital filter means, including first and second component filters, each of said component filters having a respective tapped delay line, for processing the data signal component of the third digital data signal in accordance with a programmed transfer function to produce a first filtered signal; means, coupled to the two-dimensional filter for delaying the timing signal component of the third digital data signal to compensate for processing delays incurred by the filtering of the third digital data signal; means coupled to the filter means to receive the filtered signal and an unfiltered signal provided by the tapped delay line of the first component filter and responsive to a second control signal to selectively combine the filtered signal and the unfiltered signal to produce a second filtered signal; and control means, responsive to a programming signal to generate the first and second control signals.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Pyramid processor integrated circuit 원문보기

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