이 특허를 인용한 특허 (113)

1. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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2. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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3. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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4. Ramchandran, Amit, Adaptable datapath for a digital processing system.

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5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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7. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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8. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.

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9. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.

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10. Donovan, Robert John; Godtland, Paul Lu Verne; McMeeking, Sherri Lynn; Reynolds, Joseph Patrick; Robinson, Scott Thomas; Roediger, Robert Ralph; Schmidt, William Jon; Southwick, Roger Wayne, Adaptively generating code for a computer program.

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11. Clegg, Jason Alan; Graham, Charles Scott; Lambeth, Shawn Michael; Van Grinsven, Gene Steven, Apparatus and method for adaptive address-based historical utilization recording.

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12. Master, Paul L.; Uvacek, Bohumir, Apparatus and method for adaptive multimedia reception and transmission in communication environments.

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13. Huang Yennun, Apparatus and method for fault-tolerant computing.

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14. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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15. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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16. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements.

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17. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.

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18. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.

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19. Lehr, Douglas Lee; McCune, Franklin Emmert; Reed, David Charles; Smith, Max Douglas, Apparatus, system, and method for enqueue prioritization.

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20. Ellis, Frampton Erroll, Commercial distributed processing by personal computers over the internet.

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21. Heidari, Ghobad; Chang, Kuor Hsin; Master, Paul L.; Hogenauer, Eugene B.; Scheuermann, Walter James, Communications module, device, and method for implementing a system acquisition function.

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22. Ellis, Frampton E., Computer and microprocessor control units that are inaccessible from the internet.

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23. Ellis, Frampton E., Computer or microchip controlled by a firewall-protected master controlling microprocessor and firmware.

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24. Ellis, Frampton E., Computer or microchip including a network portion with RAM memory erasable by a firewall-protected master controller.

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25. Ellis, Frampton E., Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor.

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26. Ellis, Frampton E., Computer or microchip with a secure system BIOS and a secure control bus connecting a central controller to many network-connected microprocessors and volatile RAM.

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27. Ellis, Frampton E., Computer or microchip with a secure system bios having a separate private network connection to a separate private network.

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28. Ellis, Frampton E., Computer or microchip with an internal hardware firewall and a master controlling device.

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29. Ellis, Frampton E., Computer or microchip with its system bios protected by one or more internal hardware firewalls.

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30. Ellis, Frampton E., Computer with at least one faraday cage and internal flexibility sipes.

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31. Ellis, III, Frampton E., Computers and microchips with a faraday cage, a side protected by an internal hardware firewall and an unprotected side connected to the internet for network operations, and with internal hardware compartments.

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32. Ellis, Frampton E., Computers and microchips with a faraday cage, with a side protected by an internal hardware firewall and unprotected side connected to the internet for network operations, and with internal hardware compartments.

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33. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewall.

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34. Ellis, III, Frampton E., Computers and microchips with a portion protected by an internal hardware firewalls.

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35. Ellis, III, Frampton E., Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.

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36. Ellis, III, Frampton Erroll, Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network.

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37. Ellis, Frampton E., Computers including an undiced semiconductor wafer with Faraday Cages and internal flexibility sipes.

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38. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall and an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary inner hardware firewalls.

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39. Ellis, III, Frampton E., Computers or microchips with a hardware side protected by a primary internal hardware firewall leaving an unprotected hardware side connected to a network, and with multiple internal hardware compartments protected by multiple secondary interior hardware firewalls.

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40. Ellis, Frampton E., Computers or microchips with a primary internal hardware firewall and with multiple internal harware compartments protected by multiple secondary interior hardware firewalls.

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41. Ur, Shmuel; Margalit, Mordehai; Maytal, Benjamin; Dabija, Vlad Grigore; Meir, Noam, Computing device performance monitor.

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42. Cockx, Johan; Verkest, Diederik, Concurrent timed digital system design method and environment.

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43. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.

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44. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.

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45. Furtek, Frederick Curtis; Master, Paul L., External memory controller.

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46. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.

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47. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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48. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.

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49. Ellis, Frampton E., Global network computers.

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50. Ellis, III, Frampton E., Global network computers.

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51. Ellis, III,Frampton E., Global network computers.

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52. Ellis, III,Frampton E., Global network computers.

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53. Ellis,Frampton E, Global network computers.

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54. Gulick, Dale E., Hardware enforcement mechanism for an isochronous task scheduler.

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55. Scheuermann,Walter James, Hardware implementation of the secure hash standard.

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56. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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57. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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58. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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59. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.

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60. Brandt, Scott A.; Golding, Richard A.; Wong, Theodore M, Integration of dissimilar job types into an earliest deadline first (EDF) schedule.

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61. Ellis, III, Frampton E., Internal hardware firewalls for microchips.

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62. Dale E. Gulick, Interrupt driven isochronous task scheduler system.

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63. Dale E. Gulick, Isochronous system using certified drivers to ensure system stability.

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64. Dale E. Gulick, Isochronous task scheduling structure for a non-real-time operating system.

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65. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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66. Sambhwani, Sharad; Heidari, Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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67. Sambhwani,Sharad; Heidari,Ghobad, Low I/O bandwidth method and system for implementing detection and identification of scrambling codes.

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68. Gulick,Dale E.; Helms,Frank P.; Hewitt,Larry D.; Hughes,William A.; Miranda,Paul C.; Meyer,Derrick R.; Swanstrom,Scott E.; White,Scott A., Message based power management.

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69. Helms,Frank P.; Gulick,Dale E.; Hewitt,Larry D.; Hughes,William A.; Miranda,Paul C.; Meyer,Derrick R.; Swanstrom,Scott E.; White,Scott A., Message based power management in a multi-processor system.

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70. Van Loo William C. ; Ebrahim Zahir ; Nishtala Satyanarayana ; Normoyle Kevin B. ; Kohn Leslie ; Coffin ; III Louis F., Method and apparatus for flow control in packet-switched computer system.

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71. Master, Paul L., Method and system for achieving individualized protected space in an operating system.

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72. Master, Paul L., Method and system for creating and programming an adaptive computing engine.

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73. Johns, Charles; Liu, Peichun; Omizo, Takashi, Method and system for efficient context swapping.

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74. Haughey,John, Method and system for executing multiple tasks in a task set.

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75. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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76. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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77. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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78. Plunkett, Robert T.; Heidari, Ghobad; Master, Paul L., Method and system for managing hardware resources to implement system functions using an adaptive computing architecture.

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79. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring efficiency of branch unit operation in a processing system.

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80. Levine Frank Eliot (Austin TX) Roth Charles Philip (Austin TX) Welbon Edward Hugh (Austin TX), Method and system for performance monitoring of dispatch unit efficiency in a processing system.

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81. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring of misaligned memory accesses in a processing system.

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82. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring through identification of frequency and length of time of execution of ser.

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83. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring time lengths of disabled interrupts in a processing system.

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84. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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85. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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86. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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87. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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88. Krum, Brent, Method for configuring an application server system.

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89. Jan, Mathieu; Aussagues, Christophe; David, Vincent; Lemerre, Matthieu, Method for executing, within a multitasking onboard system, an application timed according to a plurality of different time domains including interruption management.

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90. Krum, Brent, Method for job impact learning.

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91. Aussagues, Christophe; Chabrol, Damien; David, Vincent, Method for the deterministic execution and synchronization of an information processing system comprising a plurality of processing cores executing system tasks.

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92. Bhattacharya Partha Pratim ; Chung Jen-Yao ; Pirahesh Mir Hamid ; Selinger Patricia G. ; Viveros Marisa S. ; Wang Yun ; Zaino Lawrence Peter, Method of performing a parallel relational database query in a multiprocessor environment.

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93. Master,Paul L.; Hogenauer,Eugene; Wu,Bicheng William; Chuang,Dan MingLun; Freeman Benson,Bjorn, Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information.

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94. Jarvis, Thomas Charles; Lowe, Steven Robert; Werner, Sam Clark; Williams, William Dennis, Method, system, and article of manufacture for increasing processor utilization.

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95. Ellis, Frampton E., Microchip with faraday cages and internal flexibility sipes.

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96. Ellis, Frampton E, Microchips with an internal hardware firewall.

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97. Ellis, III, Frampton E., Microchips with an internal hardware firewall protected portion and a network portion with microprocessors which execute shared processing operations with the network.

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98. Ellis, III, Frampton E., Microchips with an internal hardware firewall that by its location leaves unprotected microprocessors or processing units which performs processing with a network.

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99. Ellis, Frampton E, Microchips with inner firewalls, faraday cages, and/or photovoltaic cells.

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100. Ellis, Frampton E., Microchips with multiple internal hardware-based firewalls and dies.

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101. Toshiro Yamashita JP; Toshiaki Shimoda JP; Tetsuya Takahashi JP; Kazushige Harada JP, Multiple-processor system and method for transferring data and/or a program stored in one processor to another processor in order to process the data or to execute the program therein.

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102. Ellis, III, Frampton E., Personal and server computers having microchips with multiple processing units and internal firewalls.

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103. Ellis, Frampton E., Personal computer, smartphone, tablet, or server with a buffer zone without circuitry forming a boundary separating zones with circuitry.

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104. Master, Paul L., Profiling of software and circuit designs utilizing data operation analyses.

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105. Cohn, Jonathan Daniel, Reflected interrupt for hardware-based encryption.

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106. Master,Paul L.; Watson,John, Storage and delivery of device features.

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107. Gulick, Dale E., System and method for providing a remote user with a virtual presence to an office.

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108. Master, Paul L.; Watson, John, System for adapting device standards after manufacture.

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109. Master, Paul L.; Watson, John, System for authorizing functionality in adaptable hardware devices.

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110. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.

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111. Arai, Susumi; Orita, Ryuji, Thermal management of a multi-processor computer system.

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112. Sirkin Martin Jay, Time to completion determination in a multitasking workstation.

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113. Chen, Feng (Jason); Maxwell, Matthew Scott; Sanli, Tugrul; Yao, Xiaodong, Two-part job scheduling with capacity constraints and preferences.

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