초록 ▼

A method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation

A method of fabricating an integrated circuit which maintains global planarization throughout the process flow is achieved. Trenched isolation regions are formed within a silicon substrate. Trenched polysilicon gate electrodes are formed within the silicon substrate and within the trenched isolation regions. Source and drain regions are formed within the silicon substrate wherein the top surfaces of the trenched isolation regions, the trenched polysilicon gate electrodes, and source and drain regions form a planarized top surface of the silicon substrate. A pre-metal dielectric layer is deposited over the planarized top surface. Contact openings are formed by etching through the dielectric to the trenched polysilicon gate electrodes and to the source and drain regions. The contact openings are filled with tungsten plugs wherein the top surfaces of the pre-metal dielectric and the tungsten plugs form a planarized top surface of the silicon substrate. A first metal layer is deposited over the planarized top surface. Oxygen ions are implanted into the first metal layer whereby the first metal layer is transformed into an insulator layer except where the layer is covered by photoresist wherein the top surface of the first metal layer forms a planarized top surface of the silicon substrate. The inter-metal dielectric layer and second metal layer are deposited, patterned, and planarized .

대표청구항 ▼

The method of fabricating an integrated circuit wherein global planarization is maintained throughout the process flow comprising: providing trenched isolation regions within a silicon substrate; forming trenched polysilicon gate electrodes within said silicon substrate and within said trenched isol

The method of fabricating an integrated circuit wherein global planarization is maintained throughout the process flow comprising: providing trenched isolation regions within a silicon substrate; forming trenched polysilicon gate electrodes within said silicon substrate and within said trenched isolation regions; forming source and drain regions within said silicon substrate wherein the top surfaces of said trenched isolation regions, said trenched polysilicon gate electrodes, and said source and drain regions form a planarized top surface of said silicon substrate; depositing a pre-metal dielectric layer over said planarized top surface of said silicon substrate; etching through said pre-metal dielectric to form contact openings to said trenched polysilicon gate electrodes and to said source and drain regions; filling said contact openings with metal plugs wherein the top surfaces of said pre-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a first metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into portions of said first metal layer not covered by a mask wherein said portions of said first metal layer are transformed into an insulator layer and wherein the top surface of said first metal layer forms a planarized top surface of said silicon substrate; depositing an inter-metal dielectric layer over said top planarized surface of said silicon substrate; etching through said inter-metal dielectric to form contact openings to said first metal layer; filling said contact openings with metal plugs wherein the top surfaces of said inter-metal dielectric and said metal plugs form a planarized top surface of said silicon substrate; depositing a second metal layer over said planarized top surface of said silicon substrate; implanting oxygen ions into said portions of said second metal layer not covered by a mask wherein said second metal layer is transformed into an insulator layer and wherein the top surface of said second metal layer forms a planarized top surface of said silicon substrate; and covering said planarized top surface of said silicon substrate with a passivation layer to complete fabrication of said integrated circuit wherein global planarization is maintained throughout the process flow.