이 특허를 인용한 특허 (130)

1. Arai, Kenji; Kikuchi, Hidekazu, Basic cell of gate array semiconductor device, gate array semiconductor device, and layout method for gate array semiconductor device.

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2. Konno Hideki,JPX, Buffer circuit with wide gate input transistor.

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3. Becker, Scott T., Cell circuit and layout with linear finfet structures.

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4. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

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5. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

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6. Becker, Scott T., Circuitry and layouts for XOR and XNOR logic.

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7. Becker, Scott T.; Smayling, Michael C.; Gandhi, Dhrumil; Mali, Jim; Lambert, Carole; Quandt, Jonathan R.; Fox, Daryl, Circuits with linear finfet structures.

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8. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

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9. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

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10. Smayling, Michael C.; Becker, Scott T., Coarse grid design methods and structures.

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11. Gazdzinski, Robert F., Computerized apparatus with ingestible probe.

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12. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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13. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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14. Gazdzinski, Robert F., Computerized information collection and processing apparatus and methods.

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15. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts.

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16. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track.

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17. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit defined on two gate electrode tracks.

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18. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track.

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19. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer.

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20. Becker, Scott T.; Mali, Jim; Lambert, Carole, Cross-coupled transistor circuit including offset inner gate contacts.

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21. Huang,Cheng Hsiung; Shih,Chih Ching; Tyhach,Jeffrey; Lin,Guu; Sung,Chiakang; Tran,Stephanie T., ESD protection that supports LVDS and OCT.

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22. Gazdzinski, Robert F., Endoscopic smart probe.

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23. Gazdzinski, Robert F., Endoscopic smart probe and method.

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24. Gazdzinski, Robert F., Endoscopic smart probe and method.

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25. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

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26. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

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27. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

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28. Kornachuk, Stephen; Mali, Jim; Lambert, Carole; Becker, Scott T., Enforcement of semiconductor structure regularity for localized transistors and interconnect.

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29. Becker, Scott T.; Smayling, Michael C.; Gandhi, Dhrumil; Mali, Jim; Lambert, Carole; Quandt, Jonathan R.; Fox, Daryl, Finfet transistor circuit.

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30. Colwell Michael J. (Livermore CA) Lee Teh-Kuin (San Jose CA), High density gate array base cell architecture.

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31. Gazdzinski, Robert F., Ingestible probe with agent delivery.

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32. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

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33. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

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34. Smayling, Michael C.; Becker, Scott T., Integrated circuit cell library for multiple patterning.

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35. Becker, Scott T.; Smayling, Michael C., Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length.

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36. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels.

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37. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels.

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38. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels.

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39. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel.

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40. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact.

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41. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode.

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42. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature.

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43. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature.

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44. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer.

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45. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

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46. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships.

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47. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

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48. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications.

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49. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications.

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50. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications.

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51. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications.

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52. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor.

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53. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors.

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54. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts.

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55. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors.

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56. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature.

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57. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature.

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58. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer.

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59. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer.

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60. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature.

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61. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer.

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62. Becker, Scott T.; Smayling, Michael C., Integrated circuit including gate electrode conductive structures with different extension distances beyond contact.

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63. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including gate electrode level region including cross-coupled transistors having at least one gate contact located over outer portion of gate electrode level region.

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64. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends.

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65. Becker, Scott T.; Smayling, Michael C., Integrated circuit including linear gate electrode structures having different extension distances beyond contact.

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66. Becker, Scott T.; Smayling, Michael C., Integrated circuit with gate electrode conductive structures having offset ends.

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67. Becker, Scott T.; Smayling, Michael C., Integrated circuit with offset line end spacings in linear gate electrode level.

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68. Becker, Scott T.; Mali, Jim; Lambert, Carole, Integrated circuit within semiconductor chip including cross-coupled transistor configuration.

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69. Dallavalle Carlo,ITX ; Confalonieri Pierangelo,ITX, Library of standard cells for the design of integrated circuits.

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70. Becker, Scott T.; Mali, Jim; Lambert, Carole, Linear gate level cross-coupled transistor device with non-overlapping PMOS transistors and non-overlapping NMOS transistors relative to directions of gate electrodes.

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71. Cheung Gary H. ; Lozano Elias ; Nguyen Trung ; Colwell Michael J. ; Atkinson Kevin, Low profile variable width input/output cells.

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72. Fujii,Shinji; Morimoto,Toshiki, Master slice type semiconductor integrated circuit device.

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73. Nelson,Michael D., Method for storing and shipping programmable ASSP devices.

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74. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and layouts implementing the Same.

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75. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and layouts implementing the same.

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76. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell boundary encroachment and semiconductor devices implementing the same.

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77. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

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78. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

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79. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

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80. Quandt, Jonathan R.; Becker, Scott T.; Gandhi, Dhrumil, Methods for cell phasing and placement in dynamic array architecture and implementation of the same.

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81. Reed, Brian; Smayling, Michael C.; Becker, Scott T., Methods for controlling microloading variation in semiconductor wafer layout and fabrication.

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82. Becker, Scott T.; Smayling, Michael C., Methods for designing semiconductor device with dynamic array section.

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83. Smayling, Michael C.; Becker, Scott T., Methods for linewidth modification and apparatus implementing the same.

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84. Smayling, Michael C.; Becker, Scott T., Methods for linewidth modification and apparatus implementing the same.

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85. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

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86. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

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87. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

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88. Fox, Daryl; Becker, Scott T., Methods for multi-wire routing and apparatus implementing same.

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89. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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90. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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91. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

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92. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

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93. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

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94. Smayling, Michael C.; Becker, Scott T., Methods, structures, and designs for self-aligning local interconnects used in integrated circuits.

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95. Hideki Takeuchi JP; Masami Murakata JP; Masaaki Yamada JP; Reiko Nojima JP; Takashi Ishioka JP; Mutsunori Igarashi JP, Noise suppression circuit, ASIC, navigation apparatus communication circuit, and communication apparatus having the same.

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96. Takeuchi,Hideki; Murakata,Masami; Yamada,Masaaki; Nojima,Reiko; Ishioka,Takashi; Igarashi,Mutsunori, Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same.

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97. Takeuchi,Hideki; Murakata,Masami; Yamada,Masaaki; Nojima,Reiko; Ishioka,Takashi; Igarashi,Mutsunori, Noise suppression circuit, ASIC, navigation apparatus, communication circuit, and communication apparatus having the same.

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98. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

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99. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

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100. Becker, Scott T., Oversized contacts and vias in layout defined by linearly constrained topology.

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101. Herberholz, Rainer, RF CMOS transistor design.

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102. Smayling, Michael C.; Fox, Daryl; Quandt, Jonathan R.; Becker, Scott T., Scalable meta-data objects.

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103. Smayling, Michael C.; Fox, Daryl; Quandt, Jonathan R.; Becker, Scott T., Scalable meta-data objects.

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104. Becker, Scott T.; Smayling, Michael C., Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures.

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105. Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid.

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106. Becker, Scott T.; Smayling, Michael C., Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid.

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107. Kornachuk, Stephen; Mali, James; Lambert, Carole; Becker, Scott T.; Reed, Brian, Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires.

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108. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods.

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109. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods.

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110. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods.

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111. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit defined within dynamic array section.

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112. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same.

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113. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same.

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114. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same.

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115. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same.

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116. Becker, Scott T.; Mali, Jim; Lambert, Carole, Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures.

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117. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same.

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118. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having rectangular-shaped gate structures and first metal structures.

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119. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures.

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120. Becker, Scott T.; Smayling, Michael C., Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods.

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121. Stager Mark P. ; Yee Abraham F. ; Padmanabhan Gobi R., Semiconductor chip package with interconnect layers and routing and testing methods.

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122. Mizutani Hiroshi,JPX, Semiconductor device having FETs with shared source and drain regions.

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123. Becker, Scott T.; Smayling, Michael C., Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos.

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124. Becker, Scott T.; Smayling, Michael C., Semiconductor device with gate level including gate electrode conductors for transistors of first type and transistors of second type with some gate electrode conductors of different length.

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125. Kasai Naoki,JPX, Semiconductor memory device having memory cells similarly layouted and peripheral circuits symmetrically layouted in memory cell arrays.

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126. Kato Hiroyuki (Kanagawa JPX) Ito Takaharu (Kanagawa JPX), Semiconductor semicustom-made integrated circuit device having component transistors variable in gain for forming basic.

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127. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

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128. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

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129. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

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130. Smayling, Michael C., Super-self-aligned contacts and method for making the same.

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