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Output circuit having reduced switching noise 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-017/16
출원번호 US-0035115 (1993-03-19)
우선권정보 JP-0073708 (1992-03-30)
발명자 / 주소
  • Nakao Kenji (Itami JPX)
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 42  인용 특허 : 0

초록

An output circuit which hardly causes ringing etc. in its output waveform even if a high capacity load is driven at a high speed comprises an input terminal (11), an output terminal (12), an output driving circuit (5) controlled by a signal received in the input terminal (11), and voltage drop means

대표청구항

An output circuit comprising: an input terminal being supplied with an input signal; an output terminal outputting an output signal of a first or second logical level; a power supply terminal supplying a voltage of said first logical level; resistor means having one end being connected to said outpu

이 특허를 인용한 특허 (42)

  1. Starr Jonathan E., Broadly distributed termination for buses using switched terminator logic.
  2. Deboy, Gerald; Norling, Karl, Circuit for driving a transistor dependent on a measurement signal.
  3. Deboy, Gerald, Circuit including a resistor arrangement for actuation of a transistor.
  4. Leung Wingyu ; Lee Winston ; Hsu Fu-Chieh, Data processing system with master and slave devices and asymmetric signal swing bus.
  5. Ang Michael A. ; Starr Jonathan E., Differential receiver.
  6. Loughmiller Daniel R., Drive-current modulated output driver.
  7. Wingyu Leung ; Winston Lee ; Fu-Chieh Hsu, Dynamic address mapping and redundancy in a modular memory device.
  8. Rodriguez Pablo Martin ; Townley Kent R., Dynamic circuits and static latches with low power dissipation.
  9. Ang, Michael A.; Taylor, Alexander D.; Starr, Jonathan E.; Vishwanthaiah, Sai V., Dynamic termination logic driver with improved impedance control.
  10. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Dynamic termination logic driver with improved impedance control.
  11. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Dynamic termination logic driver with improved slew rate control.
  12. Shad R. Shepston ; M. Jason Welch, Electrically adjustable pulse delay circuit.
  13. Leung, Wingyu; Hsu, Fu Chieh, Error detection/correction method.
  14. Marbot Roland (Versailles FRX) Le Bihan Jean-Claude (Montrouge FRX) Cofler Andrew (Paris FRX) Nezamzadeh-Moosavi Reza (Bois d\Arcy FRX), Impedance adaptation process and device for a transmitter and/or receiver, integrated circuit and transmission system.
  15. Vishwanthaiah Sai V. ; Starr Jonathan E. ; Taylor Alexander D., Impedance control circuit.
  16. Riad, Tamer, Impedance matching driver.
  17. Kaplinsky Cecil H., Inverter-controlled digital interface circuit with dual switching points for increased speed.
  18. Leung, Wing Yu; Hsu, Fu-Chieh, Latched sense amplifiers as high speed memory in a memory system.
  19. Hedberg Mats,SEX, Line receiver circuit having termination impedances with transmission gates connected in parallel.
  20. Singh Gajendra P., Low voltage CMOS input buffer with undershoot/overshoot protection.
  21. Leung, Wingyu; Lee, Winston; Hsu, Fu-Chieh, Memory array with read/write methods.
  22. Dorfman, Barry Lee; Rosser, Thomas Edward; Soreff, Jeffrey Paul, Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects.
  23. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Method for a dynamic termination logic driver with improved impedance control.
  24. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Method for a dynamic termination logic driver with improved slew rate control.
  25. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Method for an output driver with improved impedance control.
  26. Vishwanthaiah Sai V. ; Starr Jonathan E. ; Taylor Alexander D., Method for controlling the impedance of a driver circuit.
  27. Starr Jonathan E. ; Vishwanthaiah Sai V. ; Taylor Alexander D., Method for determining bit element values for driver impedance control.
  28. Jonathan E. Starr, Method for determining optimal configuration for multinode bus.
  29. Michael A. Ang ; Jonathan E. Starr, Method for differentiating a differential voltage signal using current based differentiation.
  30. Starr Jonathan E., Method of broadly distributing termination for buses using switched terminators.
  31. Chen, Chung-Hui, On-die terminators formed of coarse and fine resistors.
  32. Hirano, Kazutoshi, Output buffer circuit.
  33. Daniel R. Loughmiller, Output driver.
  34. Michael A. Ang ; Alexander D. Taylor ; Jonathan E. Starr ; Sai V. Vishwanthaiah, Output driver with improved impedance control.
  35. Ang Michael A. ; Taylor Alexander D. ; Starr Jonathan E. ; Vishwanthaiah Sai V., Output driver with improved slew rate control.
  36. Sakurai Naoki (Hitachi JPX) Sugawara Yoshitaka (Hitachi JPX), Power semiconductor device with low on-state voltage.
  37. Higashide, Tomofumi, Semiconductor device and communication interface circuit.
  38. Balaga, Muralikrishna; Ghatawade, Vinayak; Pradhan, Aditya, Switchable impedance drivers and related systems and methods.
  39. Leung Wingyu ; Hsu Fu-Chieh, Termination circuit with power-down mode for use in circuit module architecture.
  40. Leung Wingyu ; Lee Winston ; Hsu Fu-Chieh, Termination circuits for reduced swing signal lines and methods for operating same.
  41. Gaboriau, Johann Guy; Walburger, Eric; Melanson, John Laurence; Fei, Xiaofan, Transient noise reduction circuits, systems and methods in power digital-to-analog converters.
  42. Komatsu,Fumikazu, Transmission circuit, data-transfer control device and electronic equipment.
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