[특허]Multi-processor having control over synchronization of processors in mind mode and method of operation

Multi-processor having control over synchronization of processors in mind mode and method of operation 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/16
출원번호	US-0062867 (1993-05-17)
발명자 / 주소	Gove Robert J. (Plano TX) Balmer Keith (Bedford GB2) Ing-Simmons Nicholas K. (Bedford TX GB2) Guttag Karl M. (Missouri City TX)
출원인 / 주소	Texas Instruments Incorporated (Dallas TX 02)
인용정보	피인용 횟수 : 150 인용 특허 : 0

초록 ▼

There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).

대표청구항 ▼

A multi-processor system operable in either a single instruction multiple data (SIMD) mode, in a multiple instruction multiple data (MIMD) mode or in a synchronized multiple instruction multiple data (SMIMD) mode comprising: a synchronization bus having a plurality of bus lines; a SIMD/MIMD mode register storing therein an indication of either the single instruction multiple data (SIMD) mode or the multiple instruction multiple data (MIMD) mode; a plurality of processors, each processor having an instruction port from which each processor fetches a next instruction, a synchronization register having a plurality of bits equal in number to the number of processors, each bit corresponding to a unique one of said plurality of processors, said synchronization register having stored therein an indication of which if any other of said processors are to be synchronized with said processor when in said multiple instruction multiple data (MIMD) mode thereby indicating said synchronized multiple instruction multiple data (SMIMD) mode, an okay to synchronize circuit connected to a corresponding line of said synchronization bus for generating an okay to synchronize signal on said corresponding line of said synchronization bus when said processor is ready to fetch a next instruction, a synchronization logic unit connected to said synchronization bus, said SIMD/MIMD mode register and said synchronization register for inhibiting the fetching the next instruction until each processor indicated as to be synchronized with said processor has transmitted said okay to synchronize signal via said synchronization bus when said SIMD/MIMD mode register indicates said multiple instruction multiple data (MIMD) mode and said synchronization register indicates said synchronized multiple instruction multiple data (SMIMD) mode, and an execution unit for executing fetched instructions; plurality of instruction memories, an instruction memory corresponding to each of said processors; a switch matrix connected to said SIMD/MIMD mode register, to each of said plurality of processors and each of said instruction memories, said switch matrix including a set of first links connected to said memories, a second link having a plurality of sections equal number to the number of said processors, each section connected to said instruction port of a corresponding one said processors, a plurality of buffers connected to said SIMD/MIMD mode register and disposed between adjacent sections of said second link forming a serial chain from a first processor to a last processor, each buffer connecting said adjacent sections of said second link when said SIMD/MIMD mode register indicates the single instruction multiple data (SIMD) mode, and splitting said adjacent sections of said second link when said SIMD/MIMD mode register indicates the multiple instruction multiple data (MIMD) mode, and a plurality of crosspoints disposed at intersections between said first links and said sections of said second link, said crosspoints individually operating to connect said first links and said second link permitting said instruction port of a processor to receive an instruction from an instruction memory, said plurality of crosspoints including a first crosspoint disposed at the intersection of said section of said second link connected to said instruction more of a predetermined first processor and said first link connected to said corresponding instruction memory which is always enabled to permit connection, said plurality of crosspoints including a set of second crosspoints disposed at the intersection of each of said sections of said second link connected to said instruction port of processors other than said predetermined first processor and said respective first link connected to said corresponding instruction memories which are disabled to prohibit connection when said SIMD/MIMD register indicates the single instruction multiple data (SIMD) mode and enabled to permit connection when said SIMD/MIMD register indicates the multiple instruction multiple data (MIMD) mode.

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Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, System for biometric security using a fob.
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Breck, Lydia; Zoob, Jessica; Salow, Glen; Bishop, Fred; Schwarz, William; Glazer, Elliot; Johnstone, David; Cunningham, Katie; Nambiar, Anant; Belt, Jan Nunney; Wittwer, Martin; Armes, David; Chow, Christina, System for facilitating a transaction.
상세보기
Kimura, Scott A., System for performing finite input response (FIR) filtering in motion estimation.
상세보기
Bonalle, David; Bliman, Michal; Saunders, Peter D.; Williamson, John Robert, Systems and methods for managing account information lifecycles.
상세보기
Beenau,Blayn W.; Bliman,Michal; Bonalle,David S.; Montgomery,Joshua L.; Saunders,Peter D.; Williamson,John R., Systems and methods for managing multiple accounts on a RF transaction instrument.
상세보기
Bishop, Fred; Saunders, Peter D, Systems and methods for non-traditional payment using biometric data.
상세보기
Bonalle,David S; Fehlhaber,Jeff; Saunders,Peter D, Systems and methods for providing a RF transaction device for use in a private label transaction.
상세보기
Beenau,Blayn W.; Bliman,Michal; Bonalle,David S.; Montgomery,Joshua L.; Saunders,Peter D.; Williamson,John R., Systems and methods for providing a RF transaction device operable to store multiple distinct accounts.
상세보기
Bonalle,David S.; Fehlhaber,Jeff; Saunders,Peter D., Systems and methods for providing a RF transaction device operable to store multiple distinct calling card accounts.
상세보기
Fernando, Rex Emmanuel; Rekhter, Yakov, Technique for reducing consumption of router resources after BGP restart.
상세보기
Stuttard, Dave; Williams, Dave; O'Dea, Eamon; Faulds, Gordon; Rhoades, John; Cameron, Ken; Atkin, Phil; Winser, Paul; David, Russell; McConnell, Ray; Day, Tim; Greer, Trey, Thread manager to control an array of processing elements.
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Morrill Webb, Lisa Ann; Faenza, Jr., William J., Transaction card.
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Morrill-Webb, Lisa Ann; Faenza, Jr., William J., Transaction card.
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Beenau,Blayn W.; Bonalle,David S.; Vander Eyk,Becky; Isenberg,Susan E.; Malnati,Leigh; Mueller,Sue; Norcross,Zarita; Peart,Lee J.; Saunders,Peter D.; Skilling Belmond,Lisa; Webb,Lisa; Williamson,John, Transparent transaction device.
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Beenau, Blayn W; Bonalle, David S; Fields, Seth W; Gray, William J; Larkin, Carl; Montgomery, Joshua L; Saunders, Peter D, Voiceprint biometrics on a payment device.
상세보기
Jackson, James H.; Kraus, Thomas D., Wide connections for transferring data between PE's of an N-dimensional mesh-connected SIMD array while transferring operands from memory.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

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Multi-processor having control over synchronization of processors in mind mode and method of operation 원문보기

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Multi-processor having control over synchronization of processors in mind mode and method of operation 원문보기

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