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Apparatus and method for optimizing performance of a cache memory in a data processing system 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/02
출원번호 US-0844011 (1992-02-28)
발명자 / 주소
  • Moyer William C. (Dripping Springs TX) Arends John H. (Austin TX) White Christopher E. (Austin TX) Diefendorff Keith E. (Austin TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 62  인용 특허 : 0

초록 ▼

A circuit for allowing greater user control over a cache memory is implemented in a data processor (20). Cache control instructions have been implemented to perform touch load, flush, and allocate operations in data cache (54) of data cache unit (24). The control instructions are decoded by both ins

대표청구항 ▼

A data processor having a cache memory, comprising: an interface circuit for receiving a data processing instruction; a decoder coupled to the interface circuit for receiving and decoding the data processing instruction, the decoder decoding a first portion of the data processing instruction to prov

이 특허를 인용한 특허 (62)

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