[특허]Process for forming a multilayer wiring conductor structure in semiconductor device

Process for forming a multilayer wiring conductor structure in semiconductor device 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/443
출원번호	US-0130854 (1993-10-04)
우선권정보	JP-0264462 (1992-10-02)
발명자 / 주소	Kano Isao (Tokyo JPX)
출원인 / 주소	NEC Corporation (Tokyo JPX 03)
인용정보	피인용 횟수 : 62 인용 특허 : 0

초록 ▼

In a process for forming a multilayer wiring conductor structure, an interlayer insulator film is deposited on a surface including an upper surface of a lower layer wiring conductor, and the deposited interlayer insulator film is planarized so as to expose the upper surface of the lower layer wiring conductor. Then, a bonding metal film is deposited on a surface of the interlayer insulator film exposing the upper surface of the lower layer wiring conductor, and a photoresist film is coated on the bonding metal film and patterned. By using the patterned photoresist, a hole for formation of a connection pillar between the lower layer wiring conductor and a possible upper layer wiring conductor and a patterning of the bonding metal film are simultaneously formed. Accordingly, the bonding metal film can be formed and patterned on the upper surface of the lower layer wiring conductor without increasing the photolithography steps.

대표청구항 ▼

A process for forming a multilayer wiring conductor structure in a semiconductor device, comprising the steps of: forming a power supply film for plating on an insulator film formed on a semiconductor substrate; coating a first photoresist film on said power supply film and patterning said first photoresist film to form a first mask having a pattern for a lower layer wiring conductor formation; depositing a metal film on said power supply film by a plating process using said first mask so as to form a lower layer wiring conductor; removing said first mask; selectively removing said power supply film by using said lower layer wiring conductor as a mask; depositing a first interlayer insulator film on a surface including said lower layer wiring conductor; etching back said deposited first interlayer insulator film so as to planarize said first interlayer insulator film and to expose an upper surface of said lower layer wiring conductor; depositing a bonding metal film on a surface including said upper surface of said lower layer wiring conductor; coating a second photoresist film on said bonding metal layer and patterning said second photoresist film to form a second mask having a hole for formation of a connection pillar between said lower layer wiring conductor and a possible upper layer wiring conductor and a pattern for separation of said bonding metal film; selectively etching said bonding metal film by using said second mask so as to remove said bonding metal film within said hole for formation of a connection pillar and to remove said bonding metal film from a region other than a region above said lower layer wiring conductor; depositing a metal layer on said lower layer wiring conductor film within said hole for formation of a connection pillar by a plating process using said second mask so as to form a connection pillar between said lower layer wiring conductor and a possible upper layer wiring conductor; removing said second mask; depositing a second interlayer insulator film on a surface including said connection pillar; etching back said second interlayer insulator film so as to planarize said second interlayer insulator film and to expose an upper surface of said connection pillar; and selectively forming on said second interlayer insulator film a metal film so as to form an upper layer wiring conductor in contact with said upper surface of said connection pillar.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Process for forming a multilayer wiring conductor structure in semiconductor device 원문보기

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Process for forming a multilayer wiring conductor structure in semiconductor device 원문보기

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연구과제 타임라인

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