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Method and apparatus for placing an integrated circuit chip in a reduced power consumption state 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/00
출원번호 US-0053296 (1993-04-26)
발명자 / 주소
  • Volk Andrew M. (Loomis CA)
출원인 / 주소
  • Intel Corporation (Santa Clara CA 02)
인용정보 피인용 횟수 : 183  인용 특허 : 0

초록 ▼

A method and apparatus for a chip to monitor its own activity and enter and exit a state of reduced power consumption. The present invention includes defining a predetermined state in which the chip could power down cleanly and monitoring the chip to determine when the chip is in that predetermined

대표청구항 ▼

An integrated circuit chip for use in a computer system comprising: core logic to perform a specific function: non-core logic coupled to the core logic, wherein the non-core logic comprises a first logic circuit to store status of the integrated circuit: a second logic circuit coupled to the core lo

이 특허를 인용한 특허 (183)

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