이 특허를 인용한 특허 (66)

1. Eker, Mehmet Mustafa; Do, Viet; Pang, Simon, Adaptive phase-locked loop (PLL) multi-band calibration.

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2. Lukes Eric John ; Strom James David ; Woeste Dana Marie, Automatically ranging phase locked loop circuit for microprocessor clock generation.

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3. Martines, Ignazio; Buono, Luigi, Charge pump for a nonvolatile memory with read voltage regulation in the presence of address skew, and nonvolatile memory comprising such a charge pump.

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4. Moyal, Nathan, Circuit and method for extending the usable frequency range of a phase locked loop (PLL).

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5. Shah, Prasanna C.; Kelkar, Mukul, Circuit and method for generating a clock signal.

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6. Shah, Prasanna C.; Poisner, David I., Circuit and method for generating a clock signal.

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7. Shah, Prasanna C.; Schneider, Tom J.; Volk, Andrew M.; Kelkar, Mukul, Circuit and method for generating a clock signal.

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8. Voth David W. (Woodinville WA), Circuit for generating a low power CPU clock signal.

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9. Esaki Takafumi,JPX, Digital PLL circuit and clock generation method.

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10. Michimasa Yamaguchi JP; Tetsuya Oota JP, Digital phase locked loop capable of suppressing jitter.

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11. Larsson Patrik, Digital phase selection circuitry and method for reducing jitter.

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12. Hayashi Yasuhiro,JPX ; Mitani Kouichi,JPX, Disk reproducing apparatus having active wide-range PLL device.

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13. Hayashi Yasuhiro,JPX ; Mitani Kouichi,JPX, Disk reproducing apparatus having active wide-range PLL device.

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14. Yasuhiro Hayashi JP; Kouichi Mitani JP, Disk reproducing apparatus having active wide-range PLL device.

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15. Sawada Masayuki,JPX, Display device, and display control method and apparatus therefor.

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16. Leizerovich Gustavo D. ; Yeh Peter J., Dual band VCO with improved phase noise.

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17. Li, Wei; Bryan, Thomas Clark; Dang, Harry Huy; Eker, Mehmet Mustafa, Dual voltage-controlled oscillator structure with powder-down feature.

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18. Martin Chris G. (Boise ID), Frequency-variable oscillator controlled high efficiency charge pump.

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19. Lindstrom, Mats; Terry, Brian K., Fully integrated broadband tuner.

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20. Lindstrom,Mats; Terry,Brian K., Fully integrated broadband tuner.

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21. Kawakami Takaaki,JPX, Horizontal oscillation circuit capable of changing frequency.

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22. Kawakami Takaaki,JPX, Horizontal oscillation circuit capable of changing frequency.

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23. Duncan, Ralph; Kwan, Tom W., Integrated VCO having an improved tuning range over process and temperature variations.

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24. Duncan,Ralph; Kwan,Tom W., Integrated VCO having an improved tuning range over process and temperature variations.

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25. Noboru,Mitsuhiro; Isoda,Hiroshi; Amano,Shinji, Integrated circuit and receiving device.

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26. Wakayama, Myles; Jantzi, Stephen A.; Kim, Kwang Young; Cheung, Yee Ling Felix; Tong, Ka Wai, Low jitter high phase resolution PLL-based timing recovery system.

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27. Martin Frederick L. (Plantation FL) Carralero Cesar W. (Hialeah FL), Method and apparatus for controlling a voltage controlled oscillator tuning range in a frequency synthesizer.

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28. Tetzlaff,David E.; Goetting,F. Erich; Young,Steven P.; Hassoun,Marwan M.; Robinson,Moises E., Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit.

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29. Avanic Branko ; McKinney John K. ; Poggiali Frank A., Method and apparatus for reducing phase noise in a voltage controlled oscillator circuit.

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30. Cave Michael (Pflugerville TX), Method and apparatus for regulated low voltage charge pump.

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31. Peusens,Herbert; Clemens,Klaus, Method for driving a receiver stage and respective apparatus.

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32. Peusens, Herbert; Clemens, Klaus, Method of driving a receiver stage and respective apparatus.

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33. Dai, Liang; Lewis, Brandon Wayne; Bridges, Jeffrey Todd; Chen, Weihua, Methods and apparatus for dynamic frequency scaling of phase locked loops for microprocessors.

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34. Dvorak, Mark D., Multi-band voltage controlled oscillator.

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35. Ries, Christian, Multiband frequency generation using a single PLL-circuit.

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36. Jacob, Stefan; Peisl, Martin; Zweck, Harald, Multiple delay locked loop integration system and method.

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37. Kikuchi, Haruhide, Multiplied clock generating circuit.

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38. Vu,Roxanne; Nguyen,Huy; Lau,Benedict, PLL and method for providing a single/multiple adjustable frequency range.

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39. Kaneko,Makoto; Nakamura,Satoshi, PLL circuit with deadlock detection circuit.

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40. Hao, Jianbin; Zhu, Ning; Ke, Yanjing, PLLS covering wide operating frequency ranges.

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41. Hasegawa,Atsushi; Aoki,Tetsuya; Yamashita,Takeshi, Phase frequency synchronism circuitry and optical receiver.

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42. Mizuno Masayuki (Tokyo JPX), Phase lock loop having a reduced synchronization transfer period.

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43. Yoshida, Seiichiro; Sawada, Akihiro, Phase locked loop circuit and wireless communication system.

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44. Yeung Pak-Ho ; Wong Kern Wai ; Lewicki Laurence D., Phase locked loop fractional pulse swallowing frequency synthesizer.

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45. Moyal,Nathan; Mitchell,Eric; Gehring,Mark, Phase locked loop operable over a wide frequency range.

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46. Yao Chingchi, Phase locked loop with multiple, programmable, operating frequencies, and an efficient phase locked loop layout method.

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47. Muench, Paul D.; Prasad, Mangal; Smith, III, George E.; Sperling, Michael A., Phase locked loop with startup oscillator and primary oscillator.

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48. Nakanishi Jingo,JPX ; Nakase Yasunobu,JPX, Phase-locked loop circuit and voltage-controlled oscillator capable of producing oscillations in a plurality of frequency ranges.

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49. Chang, Horng-Der, Phase-locked loop circuit capable of adjusting the frequency range of spread spectrum clock.

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50. Bereza, William W.; Patel, Rakesh H., Phase-locked loop circuitry with multiple voltage-controlled oscillators.

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51. Wurzer, Steven G., Programmable phase-locked loop.

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52. Burgess,Paul, Radio transceiver having a phase-locked loop circuit.

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53. Burgess,Paul, Radio transceiver having a phase-locked loop circuit.

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54. Ninomiya, Shuichi, Receiver capable of selecting optimal voltage controlled oscillator.

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55. Lee,Kwon Cheol; Park,Sang Sin, Ring oscillator setting apparatus and method depending on environmental changes of an image formation apparatus.

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56. McKinney John K. ; Cruger Lorenzo ; Avanic Branko, Self-tuning and temperature compensated voltage controlled oscillator.

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57. Yamanaka Tadao,JPX ; Nakagawa Shinichi,JPX, Semiconductor device for controlling a delay time of an output signal of a PLL.

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58. Hayashi, Yasuhiro, Signal processing circuit having a voltage controlled oscillator capable of continuously changing the center frequency in accordance with a control voltage.

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59. Anders S. Nielsen DK; Pia Thomsen DK, Switchable up-conversion loop for a transmitting stage of a mobile phone.

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60. Harnishfeger, David B.; Brueske, Daniel E.; Martin, Frederick L., System and method for coarse tuning a phase locked loop (PLL) synthesizer using 2-PI slip detection.

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61. Ralph Duncan ; Tom W. Kwan, System and method for narrow band PLL tuning.

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62. Damgaard,Morten; Domino,William J.; Magoon,Rahul; Molnar,Alyosha C.; Zachan,Jeff, System for controlling the frequency of an oscillator.

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63. Caresosa,Mario; Kocaman,Namik, Transceiver system and method supporting multiple selectable voltage controlled oscillators.

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64. Fukuda Shinichi,JPX, Variable frequency ring oscillator and phase locked loop circuit to which the ring oscillator is adapted.

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65. Atesoglu, Ali, Voltage-controlled-oscillator circuitry with power supply noise rejection.

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66. Chen Oscal Tzyh-Chiang,TWX ; Sheen Robin Ruey-Bin,TWX, Wide-range and low-power consumption voltage-controlled oscillator.

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