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Manufacturing method for semiconductor devices with source/drain formed in substrate projection. 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/265
  • H01L-029/06
  • H01L-021/76
출원번호 US-0009747 (1993-01-27)
우선권정보 JP-0017176 (1992-01-31); JP-0017177 (1992-01-31); JP-0150682 (1992-06-10)
발명자 / 주소
  • Tada Yoshihide (Chiba JPX) Kunitomo Hiroyasu (Chiba JPX)
출원인 / 주소
  • Kawasaki Steel Corporation (Kobe JPX 03)
인용정보 피인용 횟수 : 103  인용 특허 : 0

초록 ▼

A projection is formed in a substrate by anisotropic etching and a transistor is contained in the projection. The central portion of the projection covered with a gate electrode is formed as a channel region, and drain and source regions are formed on both sides of the projection by oblique ion impl

대표청구항 ▼

A method of making a semiconductor device which includes at least one projection formed on a substrate having a conductivity type, the at least one projection including at least one vertical MOS transistor having a channel region, a source region and a drain region, the method comprising the steps o

이 특허를 인용한 특허 (103)

  1. Radosavljevic,Marko; Majumdar,Amlan; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark L.; Brask,Justin K.; Shah,Uday; Datta,Suman; Chau,Robert S., Block contact architectures for nanoscale channel transistors.
    상세보기
  2. Lindert, Nick; Cea, Stephen M., Bulk non-planar transistor having strained enhanced mobility and methods of fabrication.
    상세보기
  3. Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
    상세보기
  4. Ohmi, Tadahiro; Kotani, Koji; Sugawa, Shigetoshi, Complementary MIS device.
    상세보기
  5. Ohmi,Tadahiro; Kotani,Koji; Sugawa,Shigetoshi, Complementary MIS device.
    상세보기
  6. Brask, Justin K.; Datta, Suman; Doczy, Mark L.; Blackwell, James M.; Metz, Matthew V.; Kavalieros, Jack T.; Chau, Robert S., Dielectric interface for group III-V semiconductor device.
    상세보기
  7. Yeo, Yee-Chia; Wang, Ping-Wei; Chen, Hao-Yu; Yang, Fu-Liang; Hu, Chenming, Doping of semiconductor fin devices.
    상세보기
  8. Bryant, Andres; Ieong, Meikei; Muller, K. Paul; Nowak, Edward J.; Fried, David M.; Rankin, Jed, Double gated transistor and method of fabrication.
    상세보기
  9. Popp,Martin; Richter,Frank; Temmler,Dietmar; Wich Glasen,Andreas, Field effect transistor and method for fabricating it.
    상세보기
  10. Radosavljevic, Marko; Datta, Suman; Doyle, Brian S.; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Majumdar, Amian; Chau, Robert S., Field effect transistor with metal source/drain regions.
    상세보기
  11. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  12. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  13. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  14. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  15. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  16. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  17. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  18. Chau, Robert S.; Datta, Suman; Kavalieros, Jack; Brask, Justin K.; Doczy, Mark L.; Metz, Matthew, Field effect transistor with narrow bandgap source and drain regions and method of fabrication.
    상세보기
  19. Anderson, Brent A.; Bryant, Andres; Nowak, Edward J., Fin device with capacitor integrated under gate electrode.
    상세보기
  20. Anderson,Brent A.; Bryant,Andres; Nowak,Edward J., Fin device with capacitor integrated under gate electrode.
    상세보기
  21. McKee, Jeffrey A., Gate device with raised channel and method.
    상세보기
  22. Nowak,Edward J., High-density FinFET integration scheme.
    상세보기
  23. Nowak, Edward J., High-density finFET integration scheme.
    상세보기
  24. Fried, David M.; Nowak, Edward J.; Rankin, Jed H., Implanted asymmetric doped polysilicon gate FinFET.
    상세보기
  25. Fried,David M.; Nowak,Edward J.; Rankin,Jed H., Implanted asymmetric doped polysilicon gate FinFET.
    상세보기
  26. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors.
    상세보기
  27. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  28. Chang, Peter L. D.; Doyle, Brian S., Independently accessed double-gate and tri-gate transistors in same process flow.
    상세보기
  29. Nishimuta, Takefumi; Miyagi, Hiroshi; Ohmi, Tadahiro; Sugawa, Shigetoshi; Teramoto, Akinobu, MIS transistor and CMOS transistor.
    상세보기
  30. Quenette, Vincent, MOS transistor.
    상세보기
  31. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
    상세보기
  32. Datta,Suman; Doyle,Brian S.; Chau,Robert S.; Kavalieros,Jack; Zheng,Bo; Hareland,Scott A., Method and apparatus for improving stability of a 6T CMOS SRAM cell.
    상세보기
  33. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  34. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  35. Brask, Justin K.; Chau, Robert S.; Datta, Suman; Doczy, Mark L.; Doyle, Brian S.; Kavalieros, Jack T.; Majumdar, Amlan; Metz, Matthew V.; Radosavljevic, Marko, Method for fabricating transistor with thinned channel.
    상세보기
  36. Uenishi Akio,JPX ; Minato Tadaharu,JPX, Method for forming high breakdown semiconductor device.
    상세보기
  37. Iwamatsu Toshiaki,JPX ; Inoue Yasuo,JPX, Method for manufacturing a vertical mosfet including a back gate electrode.
    상세보기
  38. Anderson, Brent A.; Nowak, Edward J.; Rankin, Jed H., Method of fabricating a finfet.
    상세보기
  39. Shah,Uday; Doyle,Brian S.; Brask,Justin K.; Chau,Robert S., Method of fabricating a multi-cornered film.
    상세보기
  40. Ha Hyoung C. (Kwangmyungsi KRX), Method of fabricating a thin film transistor having vertical channel.
    상세보기
  41. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
    상세보기
  42. Adkisson,James W.; Agnello,Paul D.; Ballantine,Arne W.; Divakaruni,Rama; Jones,Erin C.; Nowak,Edward J.; Rankin,Jed H., Method of fabricating semiconductor side wall fin.
    상세보기
  43. Doyle,Brian S.; Datta,Suman; Kavalieros,Jack T.; Majumdar,Amlan, Method of ion implanting for tri-gate devices.
    상세보기
  44. Chui Benjamin W. ; Kenny Thomas W., Method of making electrical elements on the sidewalls of micromechanical structures.
    상세보기
  45. Chrong Jung Lin TW; Shui-Hung Chen TW; Di-Son Kuo TW, Method of manufacture of vertical split gate flash memory device.
    상세보기
  46. Jung Lin Chrong,TWX ; Chen Shui-Hung,TWX ; Kuo Di-Son,TWX, Method of manufacture of vertical split gate flash memory device.
    상세보기
  47. Lin Chrong-Jung,TWX ; Chen Shui-Hung,TWX ; Liang Mong-Song,TWX, Method of manufacture of vertical stacked gate flash memory device.
    상세보기
  48. Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Chau, Robert S., Method of patterning a film.
    상세보기
  49. Quek Shyue Fong,MYX ; Ang Ting Cheong,SGX ; Ong Puay Ink,MYX ; Loong Sang Yee,SGX, Method to fabricate a sub-quarter-micron MOSFET with lightly doped source/drain regions.
    상세보기
  50. Brask, Justin K.; Kavalieros, Jack; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S.; Doyle, Brian S., Methods for patterning a semiconductor film.
    상세보기
  51. Manning, H. Montgomery; Parekh, Kunal R.; Basceri, Cem; Sandhu, Gurtej S., Methods of forming vertical transistor structures.
    상세보기
  52. Manning, H. Montgomery; Parekh, Kunal R.; Basceri, Cem; Sandhu, Gurtej S., Methods of forming vertical transistor structures.
    상세보기
  53. Moroz, Victor, N-channel and P-channel end-to-end finFET cell architecture.
    상세보기
  54. Doyle,Brian S; Datta,Suman; Jin,Been Yih; Zelick,Nancy M; Chau,Robert, Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow.
    상세보기
  55. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  56. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  57. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  58. Shah, Uday; Doyle, Brian S.; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  59. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  60. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  61. Shah, Uday; Doyle, Brian; Brask, Justin K.; Chau, Robert S.; Letson, Thomas A., Nonplanar device with thinned lower body portion and method of fabrication.
    상세보기
  62. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  63. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Rios, Rafael; Linton, Tom; Datta, Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  64. Hareland,Scott A.; Chau,Robert S.; Doyle,Brian S.; Rios,Rafael; Linton,Tom; Datta,Suman, Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication.
    상세보기
  65. Brask, Justin K.; Dovle, Brian S.; Kavalleros, Jack; Doczy, Mark; Shah, Uday; Chau, Robert S., Nonplanar transistors with metal gate electrodes.
    상세보기
  66. Brask,Justin K.; Doyle,Brian S.; Doczy,Mark L.; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
    상세보기
  67. Brask,Justin K.; Doyle,Brian S.; Kavalieros,Jack; Doczy,Mark; Shah,Uday; Chau,Robert S., Nonplanar transistors with metal gate electrodes.
    상세보기
  68. Chapple-Sokol Jonathan D. (Poughkeepsie NY) Subbanna Seshadri (Hopewell Junction NY) Tejwani Manu J. (Yorktown Heights NY), One dimensional silicon quantum wire devices and the method of manufacture thereof.
    상세보기
  69. Kavalieros, Jack T.; Brask, Justin K.; Doyle, Brian S.; Shah, Uday; Datta, Suman; Doczy, Mark L.; Metz, Matthew V.; Chau, Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
    상세보기
  70. Kavalieros,Jack T.; Brask,Justin K.; Doyle,Brian S.; Shah,Uday; Datta,Suman; Doczy,Mark L.; Metz,Matthew V.; Chau,Robert S., Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby.
    상세보기
  71. Shoichi Iwasa JP; Tatsuya Kawamata JP, Semiconductor device and a method of manufacturing the same.
    상세보기
  72. Takaishi, Masaru, Semiconductor device and production method therefor.
    상세보기
  73. Takaishi, Masaru, Semiconductor device production method and semiconductor device.
    상세보기
  74. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  75. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  76. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  77. Brask, Justin K.; Kavalieros, Jack; Doyle, Brian S.; Shah, Uday; Datta, Suman; Majumdar, Amlan; Chau, Robert S., Semiconductor device structures and methods of forming semiconductor structures.
    상세보기
  78. Hueting, Raymond J. E.; Hijzen, Erwin A., Semiconductor device with FET MESA structure and vertical contact electrodes.
    상세보기
  79. Ammo, Hiroaki, Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus.
    상세보기
  80. Ammo, Hiroaki, Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus.
    상세보기
  81. Ammo, Hiroaki, Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus.
    상세보기
  82. Balasinski, Artur P.; Huang, Kuei-Wu, Spacer-type thin-film polysilicon transistor for low-power memory devices.
    상세보기
  83. Hudait, Mantu K.; Shaheen, Mohamad A.; Chow, Loren A.; Tolchinsky, Peter G.; Fastenau, Joel M.; Loubychev, Dmitri; Liu, Amy W. K., Stacking fault and twin blocking barrier for integrating III-V on Si.
    상세보기
  84. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  85. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  86. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  87. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  88. Rakshit, Titash; Giles, Martin; Pillarisetty, Ravi; Kavalieros, Jack T., Stress in trigate devices using complimentary gate fill materials.
    상세보기
  89. Choi Jong M. (Seoul KRX) Kim Jong K. (Chungcheongbuk-do KRX), Structure and fabrication method for a thin film transistor.
    상세보기
  90. Evans Jonathan Leslie,GBX, Trench gated power device fabrication by doping side walls of partially filled trench.
    상세보기
  91. Uenishi Akio,JPX ; Minato Tadaharu,JPX, Trenched high breakdown voltage semiconductor device.
    상세보기
  92. Chau, Robert S.; Doyle, Brian S.; Kavalieros, Jack; Barlage, Douglas; Datta, Suman, Tri-gate devices and methods of fabrication.
    상세보기
  93. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
    상세보기
  94. Chau,Robert S.; Doyle,Brian S.; Kavalieros,Jack; Barlage,Douglas; Datta,Suman, Tri-gate devices and methods of fabrication.
    상세보기
  95. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
    상세보기
  96. Hareland, Scott A.; Chau, Robert S.; Doyle, Brian S.; Datta, Suman; Jin, Been-Yih, Tri-gate transistor device with stress incorporation layer and method of fabrication.
    상세보기
  97. Yu,Bin; Ahmed,Shibly S.; Wang,Haihong, Varying carrier mobility in semiconductor devices to achieve overall design goals.
    상세보기
  98. Oh, Chang-Woo; Park, Dong-Gun; Lee, Sung-Young; Choe, Jeong-Dong; Kim, Dong-Won, Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same.
    상세보기
  99. Cronin John Edward ; Gortych Joseph Edward, Vertical mask for defining a region on a wall of a semiconductor structure.
    상세보기
  100. Lin, Chrong Jung; Chen, Shui-Hung; Kuo, Di-Son, Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions.
    상세보기
  101. Lin, Chrong-Jung; Chen, Shui-Hung; Liang, Mong-Song, Vertical stacked gate flash memory device.
    상세보기
  102. Chung, Woo Young, Vertical transistor of semiconductor device and method for forming the same.
    상세보기
  103. Chung, Woo Young, Vertical transistor of semiconductor device and method for forming the same.
    상세보기

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