이 특허를 인용한 특허 (43)

1. Hoffberg, Steven M.; Hoffberg-Borghesani, Linda I., Alarm system controller and a method for controlling an alarm system.

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2. Schmidt, Jens Anton Thomsen, Apparatus and method for providing round-robin arbitration.

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3. Ansari, Ahmad R.; Applebaum, Jeffery H.; Shenoy, Kunal R., Arbitration for an embedded processor block core in an integrated circuit.

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4. Scandurra, Alberto; Pisasale, Salvatore, Arbitration method and circuit architecture therefore.

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5. Wang,Dongyan, Architecture for home network on world wide web.

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6. Wang,Dongyan, Architecture for home network on world wide web with private-public IP address/URL mapping.

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7. Galijasevic, Zijad; Ancelle, Antonin; Belge, Murat, Automatic prioritization of interrupts in a modeling environment.

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8. Dutton Drew J., Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority.

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9. Gulick Dale E., Bus arbiter including aging factor counters to dynamically vary arbitration priority.

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10. Hewitt Larry D. ; Swanstrom Scott E., Bus arbiter including programmable request latency counters for varying arbitration priority.

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11. Hooks Douglas A. ; Dutton Drew J., Bus arbiter method and system.

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12. Dutton Drew J., Computer system including a plurality of real time peripheral devices having arbitration control feedback mechanisms.

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13. Witt David B. ; Pflum Marty L., Conditional latching mechanism and pipelined microprocessor employing the same.

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14. Wang,Dongyan; Humpleman,Richard, Device communication and control in a home network connected to an external network.

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15. Humpleman, Richard; Wang, Dongyan, Device customized home network top-level information architecture.

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16. Humpleman, Richard; Wang, Dongyan, Device discovery and configuration in a home network.

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17. Humpleman,Richard; Wang,Dongyan, Device discovery and control in a bridged home network.

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18. Gafken Andrew H. ; Bennett Joseph A. ; Poisner David I., Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number.

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19. Huang Paul,TWX ; Tseng Huan-Pin,TWX ; Wang Yao-Tzung,TWX ; Chang Tai-Chung,TWX ; Fan Kuo-Yen,TWX, Fair data bus arbitration system which assigns adjustable priority values to competing sources.

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20. O'Brien Rita M., Heuristic bus access arbiter.

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21. Litzenberger Paul D. (Wylie TX) Gottlieb Louis G. (Colorado Springs CO), High speed interface in a telecommunications network.

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22. Wang, Dongyan; Humpleman, Richard, Home network device information architecture.

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23. Sumihiro,Hiroshi, Information processing apparatus, information processing method, recording medium and program.

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24. Park, Hee-Chul, Interrupt signal processing circuit for sending interrupt requests to a computer system.

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25. Chowdhuri, Bhaskar, Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors.

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26. Chowdhuri, Bhaskar, Method and apparatus for dynamically granting access of a shared resource among a plurality of requestors.

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27. Joseph Jeddeloh, Method and apparatus for efficient bus arbitration.

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28. Wahler,Richard E., Method and apparatus for handling interrupts.

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29. Spratt Michael Peter,GBX ; Sharon Oran,ILX, Method and apparatus for prioritized transmission of data over a network.

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30. Dobbins Timothy M. ; Bogin Zohar, Method and apparatus for transmission of signals over a shared line.

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31. Humpleman,Richard; Wang,Dongyan, Method and apparatus for universally accessible command and control information in a network.

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32. Hur,Ibrahim, Method and system for creating and dynamically selecting an arbiter design in a data processing system.

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33. Richard Humpleman ; Dongyan Wang, Method and system for device to device command and control in a network.

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34. Ries,Gilles; Agaesse,Jean Fran��ois, Method for arbitrating access to a shared resource.

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35. Pezzini,Saverio, Method for generating interrupt commands in a microprocessor system and relative priority interrupt controller.

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36. Joseph Jeddeloh, Method of bus arbitration using requesting device bandwidth and priority ranking.

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37. O'Brien Rita M., Multimedia system employing timers to properly allocate bus access.

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38. Gehman Judy M., Priority arbiter with shifting sequential priority scheme.

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39. Sekiyama, Hiroyuki, Processing device, method of determining internal configuration of processing device, and processing system.

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40. Kethareswaran, Harendran; Rao, Amit, Resource arbiter.

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41. Horst Robert W. ; Watson William J. ; Sonnier David P., Routing arbitration for shared resources.

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42. Maleck, Timothy C., System and method for implementing a multi-level interrupt scheme in a computer system.

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43. Lambrecht J. Andrew ; Hartmann Alfred C., Variable latency and bandwidth communication pathways.

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