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Programmable logic array having programmable output driver drive capacity

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H03K-019/092
  • H03K-019/173
출원번호 US-0098229 (1993-07-27)
우선권정보 DE-4224804 (1992-07-27)
발명자 / 주소
  • Becker Steffen (Zorneding DEX) Schmitt-Landsiedel Doris (Ottobrunn DEX) Keitel-Schulz Doris (Munich DEX)
출원인 / 주소
  • Siemens Aktiengesellschaft (Munich DEX 03)
인용정보 피인용 횟수 : 56  인용 특허 : 0

초록

A programmable logic array includes configurable logic cells disposed in lines and columns. Each of the logic cells has signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output. The output driver circuit has a termin

대표청구항

A programmable logic array comprising: configurable logic cells disposed in lines and columns, each of said logic cells having signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output, said output driver circuit havi

이 특허를 인용한 특허 (56)

  1. Kuo,Wei Min; Yu,Donald Y., Apparatus for interfacing and testing a phase locked loop in a field programmable gate array.
  2. Kuo, Wei-Min; Yu, Donald Y., Apparatus for testing a phrase-locked loop in a boundary scan enabled device.
  3. Gliese, Jörg; Kamp, Winfried; Köppe, Siegmar; Scheppler, Michael, Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone.
  4. Choy Garrett ; Graf ; III W. Alfred, Asynchronous anticontention logic for bi-directional signals.
  5. Sequino, Kathy, Bench for concealing a dog cage.
  6. Sundstrom Lance L. (Pinellas Park FL), Bi-directional programmable I/O cell.
  7. Baxter Glenn A. ; Buch Kiran B. ; Pang Raymond C. ; Law Edwin S., Boundary scan chain with dedicated programmable routing.
  8. Kundu, Arunangshu; Fron, Jerome, Carry chain for use between logic modules in a field programmable gate array.
  9. Kundu, Arunangshu, Clock tree network in a field programmable gate array.
  10. Kundu, Arunangshu, Clock tree network in a field programmable gate array.
  11. Kundu,Arunangshu, Clock tree network in a field programmable gate array.
  12. Plants, William C.; Kundu, Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  13. Plants, William C.; Kundu, Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  14. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  15. Plants,William C.; Kundu,Arunangshu, Dedicated input/output first in/first out module for a field programmable gate array.
  16. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of I/O voltage levels.
  17. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of I/O voltage levels.
  18. F. Erich Goetting ; Scott O. Frake ; Venu M. Kondapalli ; Steven P. Young, FPGA with a plurality of input reference voltage levels.
  19. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of input reference voltage levels.
  20. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M. ; Young Steven P., FPGA with a plurality of input reference voltage levels grouped into sets.
  21. Plants, William C., Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array.
  22. Yu, Donald Y.; Kuo, Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
  23. Yu, Donald Y.; Kuo, Wei-Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
  24. Yu,Donald Y.; Kuo,Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
  25. Yu,Donald Y.; Kuo,Wei Min, Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers.
  26. Law Edwin S. ; Buch Kiran B. ; Baxter Glenn A. ; Pang Raymond C., Hardwire logic device emulating an FPGA.
  27. Edwin S. Law ; Kiran B. Buch ; Glenn A. Baxter ; Raymond C. Pang, Hardwire logic device emulating any of two or more FPGAs.
  28. Phillips Christopher E. (San Jose CA) Ahrens Michael G. (Sunnyvale CA) Nolan ; III Joseph G. (San Jose CA) Cooke Laurence H. (San Jose CA), Input-output circuit for increasing immunity to voltage spikes.
  29. Goetting F. Erich ; Frake Scott O. ; Kondapalli Venu M., Input/output buffer supporting multiple I/O standards.
  30. Ogawa Kyohsuke,JPX ; Tanaka Yasunori,JPX, LSI chip having programmable buffer circuit.
  31. Chan, Richard, Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays.
  32. McCollum, John, Method and apparatus for bootstrapping a programmable antifuse circuit.
  33. Vashi Mehul ; Buch Kiran, Method for verifying timing in a hard-wired IC device modeled from an FPGA.
  34. Vashi, Mehul; Buch, Kiran, Method for verifying timing in a hard-wired IC device modeled from an FPGA.
  35. Baxter Glenn A. ; Buch Kiran B. ; Pang Raymond C. ; Law Edwin S., Method of implementing a boundary scan chain.
  36. Kundu, Arunangshu; Narayanan, Venkatesh; McCollum, John; Plants, William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
  37. Kundu,Arunangshu; Narayanan,Venkatesh; McCollum,John; Plants,William C., Multi-level routing architecture in a field programmable gate array having transmitters and receivers.
  38. Plants William C. ; Bakker Gregory W., Multiple logic family compatible output driver.
  39. Aoki Takahiro,JPX ; Mitsuhashi Takashi,JPX, Output buffer, semiconductor integrated circuit having output buffer and driving ability adjusting method for output buf.
  40. Sun, Shin Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
  41. Sun, Shin-Nan; Wong, Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
  42. Sun,Shin Nan; Wong,Wayne W., Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA.
  43. Masleid, Robert Paul, Power efficient multiplexer.
  44. Masleid, Robert Paul, Power efficient multiplexer.
  45. Baxter Glenn A. ; Buch Kiran B. ; Law Edwin S., Programmable I/O cell with dual boundary scan.
  46. Eric M. Shiflet, Programmable I/O cells with multiple drivers.
  47. Baxter Glenn A. ; Buch Kiran B. ; Law Edwin S., Programmable IC with gate array core and boundary scan capability.
  48. Shieh Jhy-Jer ; Tang Dandas Kenneth, Programmable output buffer and method for programming.
  49. Yee Wilson K. (Tracy CA), Programmable scan chain testing structure and method.
  50. Kundu, Arunangshu; Sather, Eric; Plants, William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
  51. Kundu, Arunangshu; Sather, Eric; Plants, William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
  52. Kundu,Arunangshu; Sather,Eric; Plants,William C., Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks.
  53. Elftmann, Daniel; Speers, Theodore; Kundu, Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
  54. Elftmann,Daniel; Speers,Theodore; Kundu,Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
  55. Elftmann,Daniel; Speers,Theodore; Kundu,Arunangshu, Synchronous first-in/first-out block memory for a field programmable gate array.
  56. Gould Scott Whitney (Burlington VT), System for enhanced drive in programmable gate arrays.
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