[특허]Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM

Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-009/30
출원번호	US-0266900 (1994-07-01)
우선권정보	JP-0033156 (1992-02-20)
발명자 / 주소	Arakawa Fumio (Tokyo JPX) Narita Susumu (Kokubunji JPX) Uchiyama Kunio (Kodaira JPX)
출원인 / 주소	Hitachi, Ltd. (Tokyo JPX 03)
인용정보	피인용 횟수 : 24 인용 특허 : 0

초록 ▼

A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in accordance with the decoded outputs of the instruction decoders. When a high performance instruction is decoded by one of the instruction decoders, at a first step processing, one of the instruction execution units selects the output of the one instruction decoder to execute the instruction. At a second step processing, the one instruction execution unit selects a microinstruction of the microprogram ROM and executes the instruction. It is therefore unnecessary to use the microprogram ROM for the execution of a primitive instruction and a high performance instruction at the first step processing, thereby reducing the capacity, area and power consumption of the microprogram ROM.

대표청구항 ▼

A data processor comprising: an instruction fetch unit; first and second instruction decoders each for decoding an instruction supplied from said instruction fetch unit; a microprogram ROM for storing a microinstruction; a signal selector to which an output of said first instruction decoder, an output of said second instruction decoder, and an output of said microprogram ROM are input; a first instruction execution unit controlled by a first output of said signal selector; and a second instruction execution unit controlled by a second output of said signal selector, wherein a primitive instruction is executed by using both of said first and second instruction execution units one time, and when two primitive instructions are decoded by said first and second instruction decoders in parallel, said signal selector selects and outputs said outputs of said first and second instruction decoders to said first and second outputs, respectively, and said first and second instruction execution units execute said two primitive instructions in accordance with said outputs of said first and second instruction decoders transferred to said first and second outputs of said signal selector, and wherein a high performance instruction is executed by using said first instruction execution unit at least two times, and when said high performance instruction is decoded by said first instruction decoder, at a first step processing of said high performance instruction, said signal selector selects and outputs said output of said first instruction decoder to said first output and invalidates the output of said second instruction decoder and said first instruction execution unit executes said first step processing in accordance with said output of said first instruction decoder transferred to said first output of said signal selector, and at a second step processing of said high performance instruction, said signal selector selects and outputs a microinstruction of said output of said microprogram ROM to said first output and said first instruction execution unit executes said second step processing in accordance with said microinstruction of said microprogram ROM transferred to said first output of said signal selector.

이 특허를 인용한 특허 (24)

Hepworth,Paul; Powell,George, Graphical code reader that is configured for efficient decoder management.
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Worrell Frank, Interface for a modularized computational unit to a CPU.
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Kinter, Ryan C.; Courtright, David A., Mapping system and method for instruction set processing.
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Smith, Jack Robert; Ventrone, Sebastian Theodore, Method and apparatus for reducing power consumption of a processing integrated circuit.
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Narayan Rammohan ; Mahalingaiah Rupaka ; Miller Paul K., Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor.
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Narayan Rammohan ; Mahalingaiah Rupaka ; Miller Paul K., Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor.
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Dame Paul ; McClung Duane ; Newhouse Thomas J., Method for reconfiguring a wall panel system.
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Lin Derrick Chu ; Tagare Varsha P. ; Vakkalagadda Ramamohan Rao, Method for reducing peak power in dispatching instructions to multiple execution units.
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Kevin J. McGrath ; James K. Pickett, Microcode patch device and method for patching microcode using match registers and patch routines.
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Narayan Rammohan ; Mahalingaiah Rupaka ; Miller Paul K., Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions.
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Goetz John W. ; Mahin Stephen W. ; Bergkvist John J., Microprocessor with an architecture mode control capable of supporting extensions of two distinct instruction-set archi.
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Parks, Terry, Microprocessor with microtranslator and tail microcode instruction for fast execution of complex macroinstructions having both memory and register forms.
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Hurd Linda L., Power reduction for multiple-instruction-word processors by modification of instruction words.
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Ochi, Naoki, Processor, multiprocessor system, compiler, software system, memory control system, and computer system.
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Ashburn Jon L. (Fort Collins CO) Rossin Theodore G. (Fort Collins CO), Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU.
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Newhouse, Thomas J.; Martin, David B.; Breuker, Kevin Scott; Dinneweth, Mark James; Van Weiren, Steven M.; Verkaik, Thomas L., Stackable wall panel assembly and connector therefor.
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Berridge Philip Longstreet ; Compton Scott Walter ; Gezon Bruce Robert ; Lufkin Anthony David ; Ramsdell Shane Michael, Stackable wall panel system.
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Philip Longstreet Berridge ; Scott Walter Compton ; Bruce Robert Gezon ; Anthony David Lufkin ; Shane Michael Ramsdell, Stackable wall panel system.
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Paul Dame ; Duane McClung ; Thomas J. Newhouse, System of wall panels.
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Beck Robert L. ; Dame Paul ; McClung Duane ; Newhouse Thomas J. ; Norton Ronald W. ; Prisby Jim ; Schondelmayer Gerald ; Nash Sonia ; Weise Richard, Wall panel.
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Paul M. Emaus ; David B. Martin ; Richard C. Weise, Wall panel.
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Beck Robert L. ; Dame Paul G. ; De Leon Ernesto C. ; Emaus Paul M. ; Hoogland Timothy A. ; Martin David B. ; McLung Duane G. ; Newhouse Thomas J. ; Weise Richard C., Wall panel system.
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Newhouse, Thomas J.; Martin, David B.; Breuker, Kevin Scott; Dinneweth, Mark James; Van Weiren, Steven M.; Verkaik, Thomas L., Wall panel system.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
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연합인증

Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM 원문보기

초록 ▼

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Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM 원문보기

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이 특허를 인용한 특허 (24)

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