The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input
The tristate inverter of the present invention includes an input line, an output line, a first transistor for transferring a high signal to the output line, and a second transistor for transferring a low signal to the output line. The tristate inverter further includes means for isolating the input line from the second transistor, thereby significantly improving the rise time of the signal on the output line.
대표청구항▼
A tristate inverter comprising; an input line; an output line; a first transistor for transferring a signal from a low voltage source to said output line, said first transistor having a gate, a source, and a drain, said gate of said first transistor being coupled to said input line; a second transis
A tristate inverter comprising; an input line; an output line; a first transistor for transferring a signal from a low voltage source to said output line, said first transistor having a gate, a source, and a drain, said gate of said first transistor being coupled to said input line; a second transistor for transferring a signal from a high voltage source to said output line, said second transistor having a gate, a source, and a drain, said source of said second transistor being coupled to said high voltage source, said drains of said first and second transistors being coupled to said output line; and means for isolating said input line from said second transistor, wherein said means for isolating provides the high impedance state of said tristate inverter, wherein said means for isolating comprises: a third transistor having a gate, a source, and a drain, said source of said third transistor being coupled to said high voltage source; a fourth transistor having a gate, a source, and a drain, said source of said fourth transistor being coupled to said drain of said third transistor, said drain of said fourth transistor being coupled to said input line; and a fifth transistor having a gate, a source, and a drain, said drain of said fifth transistor being coupled to said source of said first transistor and said source of said fifth transistor being coupled to said low voltage source, wherein said gates of said third, fourth, and fifth transistors are coupled to a controlled signal source, and said gate of said second transistor is coupled to said drain of said third transistor.
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이 특허를 인용한 특허 (18)
Leung, Vincent, Apparatus and method for a programmable logic device having improved look up tables.
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