[특허]Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device

Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-021/90
출원번호	US-0072279 (1993-06-04)
발명자 / 주소	Jain Vivek (697 Calero St. Milpitas CA 95035) Weiling Milind G. (1265 N. Capitol Ave. #37 San Jose CA 95132) Pramanik Dipankar (1658 Jamestown Dr. Cupertino CA 95014)
인용정보	피인용 횟수 : 23 인용 특허 : 0

초록 ▼

Void-free planarization of sub-micron and deep sub-micron semiconductor devices results from depositing a layer of silicon-enriched oxide over a conventionally fabricated device and its metal traces. Conventional layers of TEOS-based oxide and SOG are then applied over the layer of silicon-enriched oxide. The silicon-enriched oxide has an index of refraction of at least about 1.50, a dangling bond density of about 1017/cm3, and is typically about 1,000 Åto 2,000 Åthick. Because it is relatively deficient in oxygen atoms, the silicon-enriched oxide releases relatively few oxygen atoms when exposed by the etching process and does not greatly accelerate the SOG etch rate. Further, the silicon-enriched oxide itself has an etch rate that is only about 75% that of stoichiometric TEOS-based oxide. As such, the silicon-enriched oxide acts as a buffer that slows the etch-back process as the etching approaches the level of the metal traces, thus protecting the metal traces against exposure. In addition, the silicon-enriched oxide advantageously promotes stability and reliability of the underlying device. The silicon-enriched performs an shield-like function by neutralizing charges that could influence the underlying semiconductor device. In practice, the silicon-enriched oxide can extend hot carrier lifetime by about one order of magnitude.

대표청구항 ▼

A method enhancing planarization etchback margin and improving reliability and stability of an integrated circuit, the method comprising the following steps: (a) forming on a substrate said integrated circuit including said at least one semiconductor device, and forming at least first and second traces at a first metal level on said substrate; (b) depositing a layer of silicon-enriched oxide over said first metal level on said substrate; (c) depositing a preliminary inter-metal oxide layer overlying said layer of silicon-enriched oxide, including (i) forming a layer of tetra-ethyl-ortho-silicade-based (“TEOS-based”) oxide and (ii) forming a layer of spin-on-glass (“SOG”) overlying said TEOS-based oxide layer; and (d) etching back said preliminary layer of inter-metal oxide to planarize said integrated circuit; wherein as step (d) approaches said first metal level, said silicon-enriched oxide slows step (d), and wherein said layer of silicon-enriched oxide improves reliability and stability of said integrated circuit by neutralizing charges and increasing hot carrier lifetime.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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연합인증

Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device 원문보기

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Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device 원문보기

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