이 특허를 인용한 특허 (42)

1. Olson, Christopher H.; Rarick, Leonard D.; Grohoski, Gregory F., Apparatus and method for implementing a hash algorithm word buffer.

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2. Olson, Christopher H.; Rarick, Leonard D.; Grohoski, Gregory F., Apparatus and method for implementing a unified hash algorithm pipeline.

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3. Masayuki Yamasaki JP, Apparatus and method of computer program control in computer systems using pipeline processing.

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4. Nakada Tatsumi (Kawasaki JPX), Apparatus for operand data bypassing having previous operand storage register connected between arithmetic input selecto.

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5. Imamura, Yoshihiko, Arithmetic processing architecture having a portion of general-purpose registers directly coupled to a plurality of memory banks.

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6. Joshi Chandra ; Rodman Paul ; Hsu Peter ; Nofal Monica R., Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions.

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7. Gazdzinski, Robert F., Computerized apparatus with ingestible probe.

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8. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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9. Gazdzinski, Robert F., Computerized information collection and processing apparatus.

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10. Gazdzinski, Robert F., Computerized information collection and processing apparatus and methods.

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11. Eickemeyer Richard James ; Malik Nadeem ; Saha Avijit, Flexible pipeline for interlock removal.

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12. Gazdzinski, Robert F., Ingestible probe with agent delivery.

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13. Joshi Chandra ; Rodman Paul ; Hsu Peter ; Nofal Monica R., Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation.

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14. Joshi, Chandra; Rodman, Paul; Hsu, Peter; Nofal, Monica R., Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution.

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15. Tsai, Richard; Liu, Xiaolei, MEMS device with integrated memory cells.

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16. Dulong Carole, Memory transfer apparatus and method useful within a pattern recognition system.

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17. Dulong Carole, Memory transfer apparatus and method useful within a pattern recognition system.

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18. Shebanow Michael C. ; Gmuender John ; Simone Michael A. ; Szeto John R. F. S. ; Maruyama Takumi ; Tovey Deforest W., Method and apparatus for selecting the oldest queued instructions without data dependencies.

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19. Olson Christopher Hans ; Brooks Jeffrey Scott, Method and system for forwarding instructions in a processor with increased forwarding probability.

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20. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring efficiency of branch unit operation in a processing system.

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21. Levine Frank Eliot (Austin TX) Roth Charles Philip (Austin TX) Welbon Edward Hugh (Austin TX), Method and system for performance monitoring of dispatch unit efficiency in a processing system.

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22. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring of misaligned memory accesses in a processing system.

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23. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring through identification of frequency and length of time of execution of ser.

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24. Levine Frank Eliot ; Roth Charles Philip ; Welbon Edward Hugh, Method and system for performance monitoring time lengths of disabled interrupts in a processing system.

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25. Afsar Muhammad (Austin TX) Mallick Soummya (Austin TX), Method for executing instructions and execution unit instruction reservation table within an in-order completion process.

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26. Machida Hirohisa,JPX, Method for generating an object code for a pipeline computer process to reduce swapping instruction set.

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27. Liu Kin-Yip ; Shoemaker Ken ; Hammond Gary ; Pai Anand ; Yellamilli Krishna, Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor.

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28. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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29. Gazdzinski, Robert F., Methods of processing data obtained from medical device.

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30. Suzuki Kazumasa,JPX ; Mohri Atsushi,JPX ; Yamada Akira,JPX ; Yoshida Toyohiko,JPX, Microprocessor for controlling the conditional execution of instructions.

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31. Curtis Steve ; Murray Robert J. ; Opie Helen, Multiported bypass cache in a bypass network.

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32. Dulong Carole, Pattern recognition system using a four address arithmetic logic unit.

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33. Nakajima Masaitsu,JPX, Pipeline data processing apparatus and method for executing a plurality of data processes having a data-dependent relati.

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34. Sowadsky Elliot A. ; Widigen Larry ; Puziol David L. ; Van Dyke Korbin S., Pipeline throughput via parallel out-of-order execution of adds and moves in a supplemental integer execution unit.

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35. Sato Toshinori,JPX, Pipelined Microprocessor and load address prediction method therefor.

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36. Sowadsky Elliot A. (Santa Clara CA) Widigen Larry (Salinas CA) Puziol David L. (Sunnyvale CA) Van Dyke Korbin S. (Fremont CA), Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add.

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37. Niot, Francois, Reduced instruction fetch latency in a system including a pipelined processor.

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38. Dhablania Atul ; Briggs Willard S., Reloadable floating point unit.

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39. Bublil Moshe ; Bose Subroto ; Gadre Shirish C. ; Ozcelik Taner, Special purpose processor for digital audio/video decoding.

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40. McDonnell,Niall D.; Wishneusky,John, Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary.

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41. Pflum Marty L., Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and anothe.

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42. Flacks, Brian King; Hofstee, Harm Peter; Takahashi, Osamu, System and method in a pipelined processor for generating a single cycle pipeline stall.

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