IPC분류정보
국가/구분 |
United States(US) Patent
등록
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국제특허분류(IPC7판) |
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출원번호 |
US-0882295
(1992-05-13)
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우선권정보 |
CN-0103198 (1991-05-17); CN-0103441 (1991-05-21); CN-0103092 (1992-04-27) |
발명자
/ 주소 |
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출원인 / 주소 |
- Duosi Software Co., Ltd. (Beijing CNX 03)
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인용정보 |
피인용 횟수 :
20 인용 특허 :
0 |
초록
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The present invention relates to a macro instruction set computer (MISC) architecture having main memory for storing system softwares of the computer, instructions, and user programs; first memory for storing preparatory data for operations, intermediate results of operations and the final results o
The present invention relates to a macro instruction set computer (MISC) architecture having main memory for storing system softwares of the computer, instructions, and user programs; first memory for storing preparatory data for operations, intermediate results of operations and the final results of completed operations, and operating in stack form; second memory for storing the break point address of subprograms and address for recovery of the break point while returning from a call, and operating in stack form; a CPU having: address management for the main memory; main memory data port for receiving instructions and data from main memory and writing data in the CPU into main memory; control logic combinational decoding for decoding instructions from main memory and generating control signals controlling the operations of the computer; ALU for performing arithmetic and logic operation functions; top of stack, next to the top of stack and the third one to the top of stack register of the first memory; top of stack register and instruction repeating execution control of the second memory; management device for the first and second memory for performing operations of writing to and reading from the first and second memory.
대표청구항
▼
A macro-instruction set computer achictecture comprising: main memory means for storing system softwares of the computer, instructions and user programs; first memory means for storing preparatory data for operation, intermediate results of operation and final results of completed operation, and ope
A macro-instruction set computer achictecture comprising: main memory means for storing system softwares of the computer, instructions and user programs; first memory means for storing preparatory data for operation, intermediate results of operation and final results of completed operation, and operating in the form of a stack; second memory means for storing a break point address of subprograms and address for recovery of a break point while returning from call, and operating in the form of a stack; and a CPU comprising: address management means for said main memory means, for forming the address for accessing said main memory means, which comprises a plurality of registers; main memory means data port for receiving instructions or data from said main memory means and writing data of the CPU into said main memory means, which comprises a plurality of registers; control logic combinational decoding means for decoding the instructions from said main memory means, and generating control signals for controlling the operation of the computer; ALU means for performing arithmetic and logic operation functions, which comprises a plurality of registers; data path focus means; square rooting means operative to directly perform hardware square rooting operation; top of stack, next to the top of stack, and a third one to the top of stack register means of said first memory means, which comprises a plurality of registers; top of stack register and instruction repeating execution control means of said second memory means, which comprises a plurality of registers; first management means for said first memory means, for performing the write-in and read-out operation of said first memory means in response to the microoperation control signal generated by instruction decoding, it comprises a plurality of registers; second management means for said second memory means for performing the write-in and read-out operation of said second memory means in response to the microoperation control signal generated by instruction decoding, which comprises a plurality of registers; system clock signal and time control signal generating means; interrupt handling means, which comprises a plurality of registers; parallel data I/O port, which comprises a plurality of registers; serial-parallel data converting I/O port, which comprises a plurality of registers; wherein, a data bus and address bus between said main memory and CPU employ wide bus structure; data path focus means collects together the data of each of the registers in said second memory means, said interrupt handling means, said top of stack register and instruction repeating execution control means of said second memory means, said serial-parallel data converting port, said parallel data I/O port, said top of stack, next to the top of stack and the third one to the top of stack register means of said first memory means, said ALU means, said main memory data port, and said address management means of said main memory means, and selects one path of data therefrom under the control of said control signal generated by instruction decoding to be sent to said ALU means to take part in operation, such that the contents of each of all the registers inside the CPU can all take part in arithmetic and logic operations; said top of stack, next to the top of stack and the third one to the top of stack registers of said first memory means are the memory stack and data processing cells located in the CPU, which are also important paths for each of the register data in the CPU, said data path focus means selects one path of data to be input to said ALU means, and after operation processing, the result is sent to said top of stack, next to the top of stack and the third one to the top of stack register means of said first memory means, while this path of data may also be sent directly to said top of stack, next to top of stack and the third one to the top of stack register means of said first memory means without operation processing, and then diverged to each of the means inside the CPU or sent to peripheral devices via said serialparallel data converting I/O port and said parallel I/O port thereby, the data transmission paths between each of the registers inside the CPU as well as between the CPU internal registers and the peripheral devices are linked up.
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