Distributed time synchronization system and method
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-007/00
H04J-003/06
출원번호
US-0089431
(1993-07-09)
발명자
/ 주소
Mincher Richard W. (San Jose CA) Lynn Kerry E. (Redwood City CA)
출원인 / 주소
Apple Computer, Inc. (Cupertino CA 02)
인용정보
피인용 횟수 :
83인용 특허 :
0
초록▼
A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard co
A distributed time synchronization system and method synchronizes nodes within a frequency hopping spread spectrum (FHSS) local area network (LAN) group to a virtual master clock value. Each node system of the present invention comprises a CPU, an input device, a display device, a printer or hard copy device, a given amount of RAM and ROM memory, a data storage device, a local clock, a transmitter/receiver, an antenna, a virtual master clock processor, and a common data bus. The method of the present invention comprises the inclusion of a node\s local clock value in a message just prior to transmission over the network, storage of a node\s local clock value in RAM after an incoming message has been received, and the calculation of the time delay between the sending node and the receiving node by the virtual master clock processor. The virtual master clock processor utilizes this time delay in maintaining a virtual master clock value, which it uses in adjusting the value of the node\s local clock at periodic intervals. This synchronizes the receiving node to the virtual master clock value. If the magnitude of the time delay exceeds a maximum allowed value, the magnitude is clamped to the maximum allowed value, thereby maintaining synchronization within a predetermined tolerance. A node can receive a message transmitted over the FHSS LAN regardless of the message address. Synchronization is therefore maintained without requiring a node to be able to communicate with any specific node within the FHSS LAN group.
대표청구항▼
A distributed time synchronization system for a wireless communications network having a plurality of node systems, each node system comprising: a display device for displaying information to the user, the display device having an input; an input device for inputting information to the system, the i
A distributed time synchronization system for a wireless communications network having a plurality of node systems, each node system comprising: a display device for displaying information to the user, the display device having an input; an input device for inputting information to the system, the input device having an output; a local clock having an input and an output for providing a timing signal, the input of the local clock for receiving a signal to adjust the local clock; a transmitter/receiver for receiving and translating radio signals into digital signals and for translating and transmitting digital signals into radio signals in response to digital control signals, the transmitter/receiver coupled to an antenna to receive and transmit radio signals, the transmitter/receiver having an input and an output for processing digital signals; a virtual master clock processing means for calculating the value of a virtual master clock for the node system, the virtual master clock processing means coupled to the transmitter/receiver, the virtual master clock processing means extracting time synchronization information from each message received over the network during a predetermined time interval and using the synchronization information extracted from each message received to calculate the value of the virtual master clock; a processing unit for adding synchronization information to each message sent by the transmitter/receiver, and for using the value of the virtual master clock to adjust the local clock, the processing unit having inputs and outputs coupled to the input device, the display device, the local clock, the transmitter/receiver and the virtual master clock processing means; and a memory for storing data and routines, the memory having inputs and outputs, the memory including a first memory area storing a routine for sending messages with time synchronization information, a second memory area storing a routine for receiving messages and storing a local clock value corresponding to each message received, and a third memory area storing a routine for adjusting the local clock using extracted synchronization information, the first and second memory areas coupled to the transmitter/receiver and the processing unit, and the third memory area coupled to the local clock and the virtual master clock processing means.
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