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In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to

In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

대표청구항 ▼

A semiconductor integrated circuit device, adopting a gate array scheme, comprising: a semiconductor substrate; a plurality of basic cells formed on a main surface of said semiconductor substrate and arranged in a first direction and in a second direction, perpendicular to said first direction, wher

A semiconductor integrated circuit device, adopting a gate array scheme, comprising: a semiconductor substrate; a plurality of basic cells formed on a main surface of said semiconductor substrate and arranged in a first direction and in a second direction, perpendicular to said first direction, wherein each of said plurality of basic cells includes p-channel MISFETs and n-channel MISFETs, said p-channel MISFETs being arranged in said first direction, said n-channel MISFETs being arranged in said first direction, and said n-channel MISFETs being arranged adjacent to said p-channel MISFETs in said second direction, wherein the p-channel and n-channel MISFETs have gate electrodes each disposed in such a manner that a gate length thereof is measured along said first direction and a gate width thereof is measured along said second direction, and wherein the p-channel and n-channel MISFETs have semiconductor regions, serving as source and drain regions thereof, formed in said semiconductor substrate; a first insulating film formed over said basic cells and said semiconductor substrate; a first wiring layer, made of a metal film and formed on said first insulating film, including first, second and third wirings, wherein said first wirings are formed over said semiconductor regions of the p-channel and n-channel MISFETs so as to cover substantially the entirety of a plan view area of said semiconductor regions and are for electrical connection to said semiconductor regions, wherein said second wirings are extended over said semiconductor regions of the p-channel and n-channel MISFETS so as to cover substantially the entire plan view area of said semiconductor regions and are provided for electrical connection to said semiconductor regions, each said second wiring extending, within said basic cell, between a respective p-channel MISFET and a respective n-channel MISFET so as to electrically connect the semiconductor region of said p-channel MISFET to the semiconductor region of said n-channel MISFET, and wherein said third wirings are electrically connected to said gate electrodes of respective ones of the p-channel and n-channel MISFETs of a basic cell in such a manner that for each such connection a respective wiring is extended from said basic cell to an adjacent basic cell in said second direction; a second insulating film formed over said first insulating film and said first wiring layer; a second wiring layer, made of a metal film and formed on said second insulating film, including first and second supply wirings and first and second signal lines each extending in said first direction; wherein said first and second supply wirings are extended, within said basic cell, over said first and second wirings so as to cover at least part of said semiconductor regions and are for electrical connection to said first wirings, said first supply wiring supplying a source voltage to said p-channel MISFETs, and said second supply wiring supplying a grounding voltage to said n-channel MISFETs, wherein said first signal lines are extended over said second wirings and are arranged between said first and second supply wirings, said first signal lines being provided for electrical connection to said second wirings, and wherein said second signal lines are formed over said third wirings and are electrically connected to said third wirings; a third insulating film formed over said second insulating film and said second wiring layer; a third wiring layer, formed of a metal film and formed on said second insulating film, including third signal lines extending in said second direction, wherein said third signal lines are extended over said plurality of basic cells and are for electrical connection to said first and second signal lines, and wherein said first, second and third signal lines are used for providing electrical connections between different ones of said plurality of basic cells.