[특허]Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness

Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-027/01 H01L-027/13
출원번호	US-0274156 (1994-07-14)
우선권정보	JP-0040496 (1992-01-31)
발명자 / 주소	Inoue Shunsuke (Yokohama JPX) Koizumi Toru (Yokohama JPX) Miyawaki Mamoru (Tokyo JPX) Sugawa Shigetoshi (Atsugi JPX)
출원인 / 주소	Canon Kabushiki Kaisha (Tokyo JPX 03)
인용정보	피인용 횟수 : 110 인용 특허 : 0

초록 ▼

A semiconductor device has an NMOS transistor and a PMOS transistor formed on at least one monocrystal Si region formed in a thin-film Si layer formed on an insulation layer. The thickness TBOX of the insulation layer on which the NMOS and PMOS transistors are formed, the voltage VSS of a low-voltage power supply and the voltage VDD of a high-voltage power supply for the NMOS and PMOS transistors satisfy a relationship expressed by the following equation: TBOX>(VDD-VSS-K2)/K1 where K1≡eBOX (QBN+QBP), K2≡2FFN+2FFP-1.03, eBOX-1 is the dielectric constant of the base insulation layer, QBN and QBP are bulk charges when the widths of depletion layers of the NMOS and PMOS transistors are maximized, and FFN and FFP are pseudo Fermi potentials of the NMOS and PMOS transistors.

대표청구항 ▼

A semiconductor device comprising an insulation layer, a thin-film Si layer formed on said insulation layer and having at least one monocrystal Si region formed therein, and an NMOS transistor and a PMOS transistor formed on said at least one monocrystal Si region, wherein a thickness TBOX of said insulation layer at a point where said NMOS and PMOS transistors are formed, a voltage VSS of a first power supply and a voltage VDD of a second power supply to be connected to said NMOS and PMOS transistors, respectively, satisfy a relationship expressed by the following inequality: TBOX>(VDD-VSSK2)/K1 where VDD>VSSK1≡eBOX-1 (QBN+QBP), K2≡2FFN+2FFP-1.03, eBOX is a dielectric constant of said base insulation layer, QBN and QBP are respective bulk charges of said NMOS and PMOS transistors when widths of depletion layers of said NMOS and PMOS transistors are maximized, and FFN and FFP are pseudo-Fermi potentials of said NMOS and PMOS transistors, respectively.

이 특허를 인용한 특허 (110)

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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연합인증

Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness 원문보기

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Silicon-on-insulator CMOS device and a liquid crystal display with controlled base insulator thickness 원문보기

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