초록 ▼

In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event

In a pipeline processor, the identities of the highest and lowest numbered registers of a subset of general registers affected by a load multiple register (LMR) instruction are stored. The number of the lowest numbered registered of the subset is incremented as the registers are loaded. In the event that a next sequential instruction requires the contents of one of the registers in the subset, the number of the required register is compared with the incremented number and the decoding phase of the next instruction is allowed to proceed when the required register has been loaded as indicated by the incremented number. The identity of the highest numbered and the next to highest numbered registers loaded by the LMR instruction are recorded in a target register and an exclusive or-circuit is provided to determine whether the total number of registers loaded by the LMR instruction is an even number or an odd number. The output of the exclusive or-circuit is used to determine whether the next-to-highest numbered register is by-passable for use in the operand fetch phase of the next instruction prior to completion of the last execution cycle of the LMR instruction.

대표청구항 ▼

A data processor comprising; a plurality of processor registers including a plurality of sequentially numbered general registers; a storage register; an instruction processing unit responsive a predefined instruction defining a sequentially numbered subset of the general registers to be loaded for s

A data processor comprising; a plurality of processor registers including a plurality of sequentially numbered general registers; a storage register; an instruction processing unit responsive a predefined instruction defining a sequentially numbered subset of the general registers to be loaded for storing in the storage register a lowest register number defining the lowest numbered register of the subset and a highest register number defining the highest numbered register of the subset and for generating, in a first time cycle, first instruction control signals for execution of the predefined instruction; and an instruction execution unit responsive to the first instruction control signals to selectively write data into the registers defined in the predefined instruction in a predetermined number of sequentially occurring time cycles and to increment the lowest number defining the lowest numbered register of the subset stored in the storage register in each of the predetermined number of time cycles; the instruction processing unit responsive to a next sequential instruction defining a specified one of the general registers to compare the number of the specified one of the general registers with the incremented lowest register number and the highest register number stored in the number register in each of the predetermined number of time cycles and generating second instruction control signals for execution of the next sequential instruction when the number of the specified one of the general registers falls outside of a range of numbers defined by the incremented lowest number and the highest number stored in the storage register.