초록 ▼

An edge transition detector for a static access memory integrated circuit provides programmable operating characteristics. The edge transition detector includes a delay line taking a state signal received on a signal line as an input and generating a delayed state signal. An exclusive-OR gate takes

An edge transition detector for a static access memory integrated circuit provides programmable operating characteristics. The edge transition detector includes a delay line taking a state signal received on a signal line as an input and generating a delayed state signal. An exclusive-OR gate takes the state signal and the delayed state signal as inputs and generating a transition pulse signal. An edge transition detector enable line connected to the exclusive-OR gate forces the output level of the exclusive-OR gate to match a predetermined logic level in a power efficient manner. An output buffer taking the transition pulse signal as its input and generating an edge detection pulse signal may also be modified to fusing, mask programming, or bonding to eliminate the edge transition detection signal.

대표청구항 ▼

An edge transition detection device, comprising: a plurality of delay lines responsive to a plurality of state signals received on a plurality of signal lines as inputs, the delay lines generating a delayed state signals; a plurality of exclusive-OR gates responsive to the state signals and the dela

An edge transition detection device, comprising: a plurality of delay lines responsive to a plurality of state signals received on a plurality of signal lines as inputs, the delay lines generating a delayed state signals; a plurality of exclusive-OR gates responsive to the state signals and the delayed state signals as inputs, the exclusive-OR gates generating a plurality of transition pulse signals; an output buffer responsive to the transition pulse signals for generating an edge detection pulse signal, the output buffer including a NOR-gate having as inputs the plurality of transition pulse signals from the plurality of exclusive-OR gates; a programmable element for fixing the edge detection pulse signal at a level indicating nonoccurrence of an edge; wherein the NOR-gate is a wired NOR-gate which comprises a plurality of transistors each receiving a transition pulse signal on a control node thereof and having a common output node, the common output node being connected to a leakage transistor for returning the common output node to a predetermined logic level; and means for selectively connecting an input node for each of the plurality of transistors of the wired NOR-gate to the predetermined logic level for suppressing generation of an edge transition pulse.