SOI CMOS device having body extension for providing sidewall channel stop and bodytie
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/00
출원번호
US-0780251
(1991-10-21)
발명자
/ 주소
Cherne, Richard D.
Clark, II, Jack E.
Dejong, Glenn A.
Lichtel, Richard L.
Morris, Wesley H.
Speece, William H.
인용정보
피인용 횟수 :
26인용 특허 :
24
초록▼
An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the
An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the body/channel region to be terminated to a prescribed bias voltage (e.g. Vss), and a channel stop region that is effective to functionally interrupt a current leakage path or `parasitic` N-channel that may be induced along sidewall surface of the P-type material of the body/channel region. In another embodiment, ionizing radiation-induced inversion of the sidewalls of the P-type body/channel region is prevented by an asymmetric sidewall channel stop structure formed in opposite end portions of the source region.
대표청구항▼
1. A mesa field effect trasistor architecture comprising: a dielectric support substrate; and a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa of a first conductivity type formed on a first
1. A mesa field effect trasistor architecture comprising: a dielectric support substrate; and a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa of a first conductivity type formed on a first surface portion of said dielectric support substrate, said body mesa having first and second sidewalls on opposite sides of said body mesa and first and second endwalls at opposite ends of said body mesa, a source mesa of a second conductivity type formed on a second surface portion of said dielectric support substrate contiguous with said first surface portion, said source mesa having third and fourth sidewalls on opposite sides of said source mesa and third and fourth endwalls at opposite ends of said source mesa, said third sidewall of said source mesa adjoining and forming a source/body junction with said first sidewall of said body mesa, and wherein said third and fourth endwalls of said source mesa adjoin no semiconductor material and are spaced apart from the first and second endwalls of said body mesa, a drain mesa of said second conductivity type formed on a third surface portion of said dielectric support substrate contiguous with said first surface portion and spaced apart from said second surface portion by said first surface portion of said dielectric support substrate, said drain mesa having fifth and sixth sidewalls on opposite sides of said drain mesa, and fifth and sixth endwalls at opposite ends of said drain mesa, said fifth sidewall of said drain mesa adjoining and forming a drain/body junction with said second sidewall of said body mesa, and wherein said fifth and sixth endwalls of said drain mesa adjoint no semiconductor material and are spaced apart from the first and second endwalls of said body mesa, and a gate layer overlying said body mesa and being operative to induce a channel in that portion of said body mesa disposed between and adjoining said source and drain mesas, and wherein said body mesa extends beyond said third endwall of said source mesa and beyond said fifth endwall of said drain mesa to said first endwall thereof as a first body mesa extension, and beyond said forth endwall of said source mesa and beyond said sixth ednwall of said drain mesa to said second endwall thereof as a second body mesa extension, and wherein a first portion of said first body mesa extension underlies said gate layer and is spaced apart from said that portion of said body mesa disposed between and adjoining said third sidewall of said source mesa and said fifth sidewall of said drain mesa by a second portion of said first body mesa extension that is located beyond said third endwall of said source mesa and beyond said fifth endwall of said drain mesa, said first portion of said first body mesa extension having a first impurity concentration greater than a second impurity concentration of said that portion of said body mesa disposed between said source and drain mesa regions, so as to form a first body mesa extension channel stop, and said second portion of said first body mesa extension having a third impurity concentration less than said first impurity concentration of said first portion of said first body mesa extension, and wherein a first portion of said second body mesa extension underlies said gate layer and is spaced apart from said that portion of said body mesa disposed between and adjoining said third sidewall of said source mesa and said fifth sidewall of said drain mesa, by a second portion of said second body mesa extenion that is located beyond said fourth endwall of said source mesa and beyond said sixth endwall of said drain mesa, said first portion of said second body mesa extension having a fourth impurity concentration greater than said second impurity concentration of said that portion of said body mesa disposed between said source and drain mesa regions, so as to form a second body mesa extension channel stop, and said second portion of said second body mesa extension having a fifth impurity concentration less than said fourth impurity concentration of said first portion of said second body mesa extension. 2. A mesa field effect transistor architecture according to claim 1, wherein said first portion of said first body mesa extension is bounded by said first endwall of said body mesa and first and second sidewall end portions of said first and second sidewalls of said body mesa which intersect said first endwall of said body mesa, and wherein said first portion of said second body mesa extension is bounded by said second endwall of said body mesa and third and fourth sidewall end portions of said first and second sidewalls of said body mesa which intersect said second endwall of said body mesa. 3. A mesa field effect transistor architecture according to claim 2, wherein said first portion of said first body mesa extension adjoins first semiconductor material of only said second portion of said first body mesa extension, and wherein said first portion of said second body mesa extension adjoins second semiconductor material of only said second portion of said second body mesa extension.
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