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SOI CMOS device having body extension for providing sidewall channel stop and bodytie

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/00
출원번호 US-0780251 (1991-10-21)
발명자 / 주소
  • Cherne, Richard D.
  • Clark, II, Jack E.
  • Dejong, Glenn A.
  • Lichtel, Richard L.
  • Morris, Wesley H.
  • Speece, William H.
인용정보 피인용 횟수 : 26  인용 특허 : 24

초록

An SOI/SOS thin film MOS mesa architecture has its body/channel region extended beyond the source and drain regions and the impurity concentration is increased at a selected portion (e.g. an end portion) of the extended body region, so as to provide both a body tie access location which enables the

대표청구항

1. A mesa field effect trasistor architecture comprising: a dielectric support substrate; and a mesa field effect transistor structure disposed on said dielectric support substrate, said mesa field effect transistor structure including a body mesa of a first conductivity type formed on a first

이 특허에 인용된 특허 (24)

  1. Black, Jimmy C., Dielectric isolation for SOI island side wall for reducing leakage current.
  2. Lu Hsindao (Dallas TX), ESD protection for SOI circuits.
  3. Calviello Joseph A. (Kings Park NY), Edge channel FET.
  4. Plus Dora (South Bound Brook NJ) Ipri Alfred C. (Hopewell Township ; Mercer County NJ), Edgeless CMOS device.
  5. Heagerty William Frederick (Norristown PA) Dillon ; Jr. Luke (Marlton NJ), Edgeless transistor.
  6. Blake Terence G. W. (Dallas TX) Lu Hsindao (Dallas TX), High performance silicon-on-insulator transistor with body node to source node connection.
  7. Matloubian Mishel (Dallas TX) Chen Cheng-Eng D. (Richardson TX) Blake Terence G. (Dallas TX), MOS transistor with improved radiation hardness.
  8. Yamaguchi Yasuo (Itami JPX) Kusunoki Shigeru (Itami JPX), MOS type field effect transistor formed on a semiconductor layer on an insulator substrate.
  9. Houston Theodore W. (Richardson TX) Pollack Gordon P. (Richardson TX), Method of fabricating a SOI transistor with pocket implant and body-to-source (BTS) contact.
  10. Rice Edward J. (Los Gatos CA), Method of fabricating mesa MOSFET using overhang mask and resulting structure.
  11. Widdershoven Franciscus P. (Eindhoven NLX), Method of manufacturing a silicon on insulator (SOI) semiconductor device.
  12. Shinohara Mahito (Tokyo JPX) Yonehara Takao (Atsugi JPX), Photoelectric conversion device.
  13. Shimada Tetsuya (Zama JPX) Itabashi Satoshi (Atsugi JPX) Hatanaka Katsunori (Yokohama JPX), Photosensor with charge storage unit and switch unit formed on a single-crystal semiconductor film.
  14. Bahraman Ali (Palos Verdes Estates CA), Radiation hardened CMOS on SOI or SOS devices.
  15. Houston Theodore W. (Richardson TX) Blake Terence G. W. (Dallas TX), SOI layout for low resistance gate.
  16. Schloetterer Heinrich (Putzbrunn-Solalinden DT) Tihanyi Jenoe (Munich DT), Schottky gate field effect transistor.
  17. Ipri Alfred C. (Hopewell Township ; Mercer County NJ) Plus Dora (South Bound Brook NJ), Semiconductor device that minimizes the leakage current associated with the parasitic edge transistors and a method of m.
  18. Ng Kwok K. (Union NJ) Sze Simon M. (Berkeley Heights NJ), Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method.
  19. Widdershoven Franciscus P. (Eindhoven NLX), Silicon on insulator (SOI) semiconductor device.
  20. Cricchi James R. (Catonsville MD) Fitzpatrick Michael D. (Glen Burnie MD), Silicon on sapphire MOS transistor.
  21. Blake Terence G. W. (Dallas TX), Silicon-on-insulator transistor with body node to source node connection.
  22. Huang Tiao-Yuan (Cupertino CA) Chiang Anne (Cupertino CA) Wu I-Wei (San Jose CA), Simultaneously deposited thin film CMOS TFTs and their method of fabrication.
  23. Hatano Hiroshi (Yokohama JPX), Stacked MOS device with means to prevent substrate floating.
  24. Jackson Thomas N. (Ossining NY), Vertical MESFET with mesa step defining gate length.

이 특허를 인용한 특허 (26)

  1. Flaker ; deceased Roy Childs ; Hsu Louis L. ; Kuang Jente B., Circuit and methods to improve the operation of SOI devices.
  2. Walker Darryl, DRAM memory cell and array having pass transistors with surrounding gate.
  3. Voldman, Steven Howard, FinFET device structure and method for forming same.
  4. Pearce Lawrence George, High efficiency quasi-vertical DMOS in CMOS or BICMOS process.
  5. Merrill Richard Billings, High-voltage MOS transistor on a silicon on insulator wafer.
  6. Erstad David Owen, L-and U-gate devices for SOI/SOS applications.
  7. Geroge E. Smith, III, Method and improved SOI body contact structure for transistors.
  8. Morris, Wesley H., Method for radiation hardening a semiconductor device.
  9. Fung, Ka Hing, Method of reducing the extrinsic body resistance in a silicon-on-insulator body contacted MOSFET.
  10. Forbes, Leonard; Noble, Wendell P., Methods, structures, and circuits for transistors with gate-to-body capacitive coupling.
  11. Leonard Forbes ; Wendell P. Noble, Methods, structures, and circuits for transistors with gate-to-body capacitive coupling.
  12. Dockerty, Robert; Haddad, Nadim; Hurt, Michael J.; Brady, Frederick T., Radiation hardened silicon-on-insulator (SOI) transistor having a body contact.
  13. Robert Dockerty ; Nadim Haddad ; Michael J. Hurt ; Frederick T. Brady, Radiation hardened silicon-on-insulator (SOI) transistor having a body contact.
  14. Chen Wei ; Sadana Devendra Kumar ; Taur Yuan, SOI CMOS structure.
  15. Tyson Scott M. ; Woodruff Richard L., SOI combination body tie.
  16. Shunpei Yamazaki JP; Takeshi Fukunaga JP, Semiconductor device.
  17. Yamazaki Shunpei,JPX ; Fukunaga Takeshi,JPX, Semiconductor device.
  18. Yamazaki, Shunpei; Fukunaga, Takeshi, Semiconductor device.
  19. Nikami, Takashi, Semiconductor device and method for fabricating the same.
  20. Yamazaki, Yasushi, Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment.
  21. Yamazaki, Yasushi, Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment.
  22. Ohkubo, Tatsuya; Kawachi, Genshiro; Mikami, Yoshiro; Masuda, Kazuhito; Kageyama, Hiroshi, Semiconductor element and liquid crystal display device using the same.
  23. Ohkubo Tatsuya,JPX ; Kawachi Genshiro,JPX ; Mikami Yoshiro,JPX ; Masuda Kazuhito,JPX ; Kageyama Hiroshi,JPX, Semiconductor element with N channel and P region connected only to the channel and liquid crystal display device using the same.
  24. Inoue, Satoshi; Yudasaka, Ichio, Thin film transistors, and liquid crystal display device and electronic apparatus using the same.
  25. Inoue, Satoshi; Yudasaka, Ichio, Thin film transistors, liquid crystal display device and electronic apparatus using the same.
  26. Choi Jae Hoon,KRX ; Koh Yo Hwan,KRX ; Hong Hyeong Sun,KRX, Transistor for providing protection from electrostatic discharge.
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