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Triple heterojunction bipolar transistor

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/082
  • H01L-029/12
  • H01L-029/167
출원번호 US-0255695 (1994-06-08)
발명자 / 주소
  • Mohammad S. Noor (Hopewell Junction NY)
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 79  인용 특허 : 0

초록

A vertical Triple Heterojunction Bipolar Transistor (THBT) and method of fabrication therefor. The THBT collector has a substrate layer of N+silicon, an N-silicon layer grown on the substrate and a Si/SiGe superlattice grown on the N-silicon layer. The THBT base is layer of P+SiGe grown on the super

대표청구항

A Heterojunction Bipolar Transistor (HBT) comprised of: a first superlattice in a collector region; a second superlattice in an emitter region; a base layer between said emitter and said collector region; and said first and said second superlattice comprising: alternating layers of a first and a sec

이 특허를 인용한 특허 (79)

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  2. Enicks,Darwin Gene; Carver,Damian, Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement.
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  7. Currie,Matthew T., Control of strain in device layers by prevention of relaxation.
  8. Currie,Matthew T., Control of strain in device layers by selective relaxation.
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  10. Fitzgerald,Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
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  12. Wang, Chih-Hsin, Electrically alterable memory cell.
  13. Lochtefeld, Anthony J.; Langdo, Thomas A.; Westhoff, Richard, Elevated source and drain elements for strained-channel heterojuntion field-effect transistors.
  14. Wu,Kenneth C.; Fitzgerald,Eugene A.; Taraschi,Gianni; Borenstein,Jeffrey T., Etch stop layer system.
  15. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.
  16. El-Sharawy El-Badawy Amien ; Hashemi Majid M., Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction.
  17. Gray,Peter B.; Johnson,Jeffrey B., High performance vertical PNP transistor method.
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  20. Chu,Jack Oon; Coolbaugh,Douglas Duane; Dunn,James Stuart; Greenberg,David R.; Harame,David L.; Jagannathan,Basanth; Johnson,Robb Allen; Lanzerotti,Louis D.; Schonenberg,Kathryn Turner; Wuthrich,Ryan , Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology.
  21. Wang, Chih Hsin, Low power electrically alterable nonvolatile memory cells and arrays.
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  24. Fitzgerald, Eugene A., Low threading dislocation density relaxed mismatched epilayers without high temperature growth.
  25. Wang, Chih-Hsin, Method and apparatus for semiconductor device and semiconductor memory device.
  26. Wang,Chih Hsin, Method and apparatus for semiconductor device and semiconductor memory device.
  27. Wang, Chih Hsin, Method and apparatus transporting charges in semiconductor device and semiconductor memory device.
  28. Wang, Chih-Hsin, Method and apparatus transporting charges in semiconductor device and semiconductor memory device.
  29. Enicks,Darwin Gene, Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement.
  30. Lee,Minjoo L.; Fitzgerald,Eugene A., Method for improving hole mobility enhancement in strained silicon p-type MOSFETS.
  31. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs.
  32. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS.
  33. Cheng,Zhiyuan; Fitzgerald,Eugene A.; Antoniadis,Dimitri A., Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers.
  34. El-Sharawy El-Badawy Amien ; Hashemi Majid M., Method of forming heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction.
  35. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  36. Fitzgerald,Eugene; Currie,Matthew, Methods for fabricating strained layers on semiconductor substrates.
  37. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming III-V semiconductor device structures.
  38. Langdo, Thomas A.; Currie, Matthew T.; Hammond, Richard; Lochtefeld, Anthony J.; Fitzgerald, Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain.
  39. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes.
  40. Wang, Chih Hsin, Methods for operating semiconductor device and semiconductor memory device.
  41. Fitzgerald, Eugene A., Methods of fabricating contact regions for FET incorporating SiGe.
  42. Vineis,Christopher; Yang,Vicky; Currie,Matthew; Westhoff,Richard; Leitz,Christopher, Methods of fabricating semiconductor heterostructures.
  43. Langdo,Thomas A.; Lochtefeld,Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.
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  46. Currie,Matthew T.; Hammond,Richard, Methods of forming reacted conductive gate electrodes.
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  49. Lochtefeld,Anthony J.; Langdo,Thomas A.; Hammond,Richard; Currie,Matthew T.; Braithwaite,Glyn; Fitzgerald,Eugene A., Methods of forming strained-semiconductor-on-insulator finFET device structures.
  50. She, Min; Wang, Chih-Hsin, Non-volatile memory cell and array.
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  58. Fitzgerald,Eugene A., Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits.
  59. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
  60. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.
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  69. Westhoff,Richard; Vineis,Christopher J.; Currie,Matthew T.; Yang,Vicky T.; Leitz,Christopher W., Semiconductor structures with structural homogeneity.
  70. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Semiconductor substrate structure.
  71. Currie,Matthew T.; Lochtefeld,Anthony J., Shallow trench isolation process.
  72. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained germanium-on-insulator device structures.
  73. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  74. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.
  75. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures with elevated source/drain regions.
  76. Langdo,Thomas A.; Currie,Matthew T.; Braithwaite,Glyn; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator finFET device structures.
  77. Larry D. McMillan ; Carlos A. Paz de Araujo ; Koji Arita ; Masamichi Azuma JP, Thin film capacitors on silicon germanium substrate.
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  79. El-Badawy Amien El-Sharawy ; Majid M. Hashemi, Vertical heterojunction bipolar transistor.
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