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Computer system with clock shared between processors executing separate instruction streams 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-015/16
출원번호 US-0326573 (1989-03-21)
우선권정보 GB-0006862 (1988-03-23); GB-0006866 (1988-03-23)
발명자 / 주소
  • Baldwin David R. (Weybridge GBX)
출원인 / 주소
  • 3DLabs Ltd (Egham GBX 03)
인용정보 피인용 횟수 : 79  인용 특허 : 0

초록 ▼

A multiprocessor system which includes a control processor and a high-level data-transfer processor. Both of these two processors are docked by a shared variable-duration clock. The duration of the clock is adjusted on the fly, to accommodate whichever of the two processors needs the longest cycle t

대표청구항 ▼

A computer system, comprising: an external interface controller, operatively connected to an external interface bus; a control processor, connected to execute a first separate respective stream of instructions; a data transfer processor, which is operable concurrently with said control processor to

이 특허를 인용한 특허 (79)

  1. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  2. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter J., Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  3. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  4. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  5. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
    상세보기
  6. Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements.
    상세보기
  7. Preetham, Arcot J.; Pomianowski, Andrew S.; Koduri, Raja, Antialiasing system and method.
    상세보기
  8. Hollis, Timothy M., Apparatus for bypassing faulty connections.
    상세보기
  9. Hollis, Timothy M., Apparatus for bypassing faulty connections.
    상세보기
  10. Kissell, Kevin D., Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor.
    상세보기
  11. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements.
    상세보기
  12. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  13. Master, Paul L.; Smith, Stephen J.; Watson, John, Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements.
    상세보기
  14. Kelley, Timothy M.; Campbell, Jonathan L.; Gotwalt, David A., Applying non-homogeneous properties to multiple video processing units (VPUs).
    상세보기
  15. Krech ; Jr. Alan S. ; Rossin Theodore G. ; Strunk Glenn W ; McGrath Michael S ; Rojas Edmundo ; Tucker S Paul ; Ashburn Jon L ; Rakel Ted, Centralized branch intelligence system and method for a geometry accelerator.
    상세보기
  16. Venus, Brian; Benavides, Nicholas D., Communications architecture for providing data communication, synchronization and fault detection between isolated modules.
    상세보기
  17. Hunkins, James; Koduri, Raja, Compositing in multiple video processing unit (VPU) systems.
    상세보기
  18. Hunkins, James; Koduri, Raja, Compositing in multiple video processing unit (VPU) systems.
    상세보기
  19. Hunkins, James; Koduri, Raja, Compositing in multiple video processing unit (VPU) systems.
    상세보기
  20. Fung Patrick Wai-Wah ; Ventrone Sebastian Theodore, Concurrent multitasking in a uniprocessor.
    상세보기
  21. Master, Paul L.; Watson, John, Configurable hardware based digital imaging apparatus.
    상세보기
  22. Boutaud Frederic (Roquefort les Pins FRX) Ehlig Peter N. (Houston TX), Devices, systems and methods for conditional instructions.
    상세보기
  23. Campbell, Jonathan L.; Ribble, Maurice, Dynamic load balancing in multiple video processing unit (VPU) systems.
    상세보기
  24. Campbell, Jonathan L.; Ribble, Maurice, Dynamic load balancing in multiple video processing unit (VPU) systems.
    상세보기
  25. Campbell, Jonathan L.; Ribble, Maurice, Dynamic load balancing in multiple video processing unit (VPU) systems.
    상세보기
  26. Nair Ravindra Kumar, Dynamically typed register architecture.
    상세보기
  27. Furtek, Frederick Curtis; Master, Paul L., External memory controller.
    상세보기
  28. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
    상세보기
  29. Furtek, Frederick Curtis; Master, Paul L., External memory controller node.
    상세보기
  30. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  31. Furtek, Fredrick Curtis; Master, Paul L., External memory controller node.
    상세보기
  32. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
    상세보기
  33. Waki, Hiroyuki; Inoue, Shinji; Hayama, Satoru; Fujita, Mitsuko; Ishikawa, Akira, High speed virtual machine and compiler.
    상세보기
  34. Ramchandran,Amit, Input pipeline registers for a node in an adaptive computing engine.
    상세보기
  35. Fukushiro Masayuki,JPX ; Nakayama Daijoh,JPX, Interpreter language processing device.
    상세보기
  36. Hollis, Timothy M., Low power multi-level signaling.
    상세보기
  37. Poulson, Steven Robert, Malware classification for unknown executable files.
    상세보기
  38. Bradbury, Jonathan D.; Gschwind, Michael K., Managing register pairing.
    상세보기
  39. Harriman David J. ; Langendorf Brian K., Method and apparatus for implementing a flush command for an accelerated graphics port device.
    상세보기
  40. Master, Paul L., Method and system for achieving individualized protected space in an operating system.
    상세보기
  41. Master, Paul L., Method and system for creating and programming an adaptive computing engine.
    상세보기
  42. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  43. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  44. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  45. Scheuermann, W. James, Method and system for reconfigurable channel coding.
    상세보기
  46. Kohashi, Yasuo; Ishida, Kenichi; Matsuo, Masatoshi; Moriiwa, Tosihiro; Fujimoto, Hitoshi, Method of designing semiconductor integrated circuit device.
    상세보기
  47. Liao, Zhiyong, Method, device and computer storage medium for implementing interface cache dynamic allocation.
    상세보기
  48. Hollis, Timothy M., Methods for bypassing faulty connections.
    상세보기
  49. Dowling,Eric M., Methods for intelligent caching in an embedded DRAM-DSP architecture.
    상세보기
  50. Hollis, Timothy M., Multi-level signaling.
    상세보기
  51. Hollis, Timothy M., Multi-level signaling.
    상세보기
  52. Rogers, Philip J.; Cheng, Jeffrey Gongxian; Semiannikov, Dmitry; Koduri, Raja, Multiple video processor unit (VPU) memory mapping.
    상세보기
  53. Schulz, Kenneth R; Rapp, John W; Jackson, Larry; Jones, Mark; Cherasaro, Troy, Pipeline accelerator having multiple pipeline units and related computing machine and method.
    상세보기
  54. Jain Sanjay (Santa Clara CA) Aatresh Deepak J. (Sunnyvale CA), Power management for low power processors through the use of auto clock-throttling.
    상세보기
  55. Bradbury, Jonathan D.; Gschwind, Michael K., Predicting register pairs.
    상세보기
  56. Kissell, Kevin D., Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor.
    상세보기
  57. Miller Kevin L. ; Hayes Stuart W., Process to allow automatic microprocessor clock frequency detection and selection.
    상세보기
  58. Genduso Thomas Basilio ; Mosley Joseph Michael, Processor with free running clock with momentary synchronization to subsystem clock during data transfers.
    상세보기
  59. Dowling,Eric M., Program controlled embedded-DRAM-DSP architecture and methods.
    상세보기
  60. Dowling, Eric M., Program controlled embedded-DRAM-DSP having improved instruction set architecture.
    상세보기
  61. Worrell, Frank, Pseudo pipeline and pseudo pipelined SDRAM controller.
    상세보기
  62. Krech ; Jr. Alan S. ; Rossin Theodore G. ; Rojas Edmundo ; McGrath Michael S ; Rakel Ted ; Strunk Glenn W ; Ashburn Jon L ; Tucker S Paul, ROM-based control unit in a geometry accelerator for a computer graphics system.
    상세보기
  63. Bradbury, Jonathan D.; Gschwind, Michael K., Reducing register read ports for register pairs.
    상세보기
  64. Bradbury, Jonathan D.; Gschwind, Michael K., Reducing register read ports for register pairs.
    상세보기
  65. Wood, Paul B., Self-timed processor.
    상세보기
  66. Oh, Se-Jang; Kang, Ki-Sang; Bang, Jeong-Ho, Semiconductor device testing system.
    상세보기
  67. Kissell, Kevin D., Software emulation of directed exceptions in a multithreading processor.
    상세보기
  68. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  69. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  70. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  71. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  72. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  73. Kissell, Kevin D., Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts.
    상세보기
  74. Kissell, Kevin D., Synchronized storage providing multiple synchronization semantics.
    상세보기
  75. Hussain, Syed Athar; Hunkins, James; Vallieres, Jacques, Synchronizing multiple cards in multiple video processing unit (VPU) systems.
    상세보기
  76. Reuter James M. ; Lamport Leslie ; Gafni Eliezer, System and method for exclusive access to shared storage.
    상세보기
  77. Kissell, Kevin D., System, method, and computer program product for conditionally suspending issuing instructions of a thread.
    상세보기
  78. Katragadda, Ramana; Spoltore, Paul; Howard, Ric, Task definition for specifying resource requirements.
    상세보기
  79. Haddock Stephen R. ; Harwood Michael J. ; Schneider Herb O., Use of video DRAM for memory storage in a local area network port of a switching hub.
    상세보기

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