이 특허를 인용한 특허 (99)

1. Hiscock, Dale, Adaptive routing to avoid non-repairable memory and logic defects on automata processor.

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2. Vadi,Vasisht Mantra, Adjustable global tap voltage to improve memory cell yield.

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3. Mar, Monte, Apparatus and method for programmable power management in a programmable analog circuit block.

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4. Sullam, Bert; Kutz, Harold; Mar, Monte; Thiagaragen, Eashwar; Williams, Timothy; Wright, David G., Autonomous control in a programmable system.

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5. Roe, Steve; Nemecek, Craig, Breakpoint control in an in-circuit emulation system.

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6. Wright, David G.; Williams, Timothy J., Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes.

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7. Cossoul,Matthieu P. H.; Bapat,Shekhar, Circuit for and method of implementing programmable logic devices.

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8. Synder, Warren; Sullam, Bert, Clock driven dynamic datapath chaining.

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9. Nemecek, Craig, Conditional branching in an in-circuit emulation system.

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10. Best, Andrew; Ogami, Kenneth; Zhaksilikov, Marat, Configuration of programmable IC design elements.

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11. Shau, Jeng-Jye, Cost saving methods using pre-defined integrated circuit modules.

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12. Chou, Deanna J.; Craig, Jesse E.; Sargis, Jr., John; Singley, Daneyand J.; Ventrone, Sebastian T., Design structure for dynamically selecting compiled instructions.

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13. Synder, Warren; Sullam, Bert, Dynamically configurable and re-configurable data path.

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14. Nemecek, Craig; Roe, Steve, External interface for event architecture.

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15. Marple David P. ; Cooke Laurence H., FPGA redundancy.

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16. Abramovici Miron ; Stroud Charles E., Fault tolerant operation of field programmable gate arrays.

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17. Pleis, Matthew A.; Ogami, Kenneth Y.; Zhaksilikov, Marat, Graphical user interface for dynamically reconfiguring a programmable device.

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18. Anderson, Doug, Graphical user interface with user-selectable list-box.

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19. May, Roger; Kostarnov, Igor; Flaherty, Edward H.; Dickinson, Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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20. May, Roger; Kostarnov, Igor; Flaherty, Edward H.; Dickinson, Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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21. May,Roger; Kostarnov,Igor; Flaherty,Edward H; Dickinson,Mark, I/O circuitry shared between processor and programmable logic portions of an integrated circuit.

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22. Nemecek, Craig; Roe, Steve, In-circuit emulator and pod synchronized boot.

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23. Seguine, Dennis R., Input/output multiplexer bus.

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24. Sequine, Dennis R., Input/output multiplexer bus.

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25. Baxter,Michael A., Meta-address architecture for parallel, dynamically reconfigurable computing.

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26. Tse, John; Carvalho, Neville, Method and apparatus for circuit block reconfiguration EDA.

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27. Abramovici Miron ; Stroud Charles Eugene ; Wijesuriya Sajitha S., Method and apparatus for testing field programmable gate arrays.

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28. Perrin, Jon; Seguine, Dennis, Method for parameterizing a user module.

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29. Stroud Charles E. ; Abramovici Miron, Method for testing field programmable gate arrays.

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30. Stroud Charles E. ; Abramovici Miron, Method for testing field programmable gate arrays.

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31. Trimberger Stephen M., Method for tolerating defective logic blocks in programmable logic devices.

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32. Kuang,Raymond, Method for using a chip carrier substrate with a land grid array and external bond terminals.

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33. Prein Frank, Method of maximizing chip yield for semiconductor wafers.

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34. Abramovici Miron ; Lee Eric Seng-Kar ; Stroud Charles Eugene, Method of testing and diagnosing field programmable gate arrays.

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35. Chou, Deanna J.; Craig, Jesse E.; Sargis, Jr., John; Singley, Daneyand J.; Ventrone, Sebastian T., Method, apparatus and computer program product for dynamically selecting compiled instructions.

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36. Trimberger, Stephen M., Methods of enabling the use of a defective programmable device.

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37. Trimberger, Stephen M., Methods of enabling the validation of an integrated circuit adapted to receive one of a plurality of configuration bitstreams.

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38. Trimberger, Stephen M.; Ehteshami, Babak, Methods of using one of a plurality of configuration bitstreams for an integrated circuit.

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39. Wells,Robert W.; Patrie,Robert D.; DeBaets,Andrew J., Methods of utilizing programmable logic devices having localized defects in application-specific products.

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40. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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41. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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42. Snyder, Warren S.; Mar, Monte, Microcontroller programmable system on a chip.

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43. Snyder, Warren, Microcontroller programmable system on a chip with programmable interconnect.

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44. Snyder, Warren S, Microcontroller programmable system on a chip with programmable interconnect.

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45. Trimberger, Stephen M., Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein.

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46. Trimberger,Stephen M., Multiple bitstreams enabling the use of partially defective programmable integrated circuits while avoiding localized defects therein.

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47. Kutz, Harold, Numerical band gap.

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48. Abramovici, Miron; Stroud, Charles E.; Emmert, John M., On-line fault tolerant operation via incremental reconfiguration of field programmable gate arrays.

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49. Abramovici, Miron; Stroud, Charles E., On-line testing of field programmable gate array resources.

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50. Abramovici, Miron; Stroud, Charles E., On-line testing of the programmable interconnect network in field programmable gate arrays.

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51. Abramovici, Miron; Stroud, Charles E., On-line testing of the programmable logic blocks in field programmable gate arrays.

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52. Snyder, Warren S.; Mar, Monte, PSOC architecture.

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53. Snyder, Warren; Mar, Monte, PSOC architecture.

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54. Snyder, Warren S.; Mar, Monte, PSoC architecture.

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55. Snyder, Warren S.; Mar, Monte, PSoC architecture.

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56. Ogami, Kenneth Y., Power management architecture, method and configuration system.

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57. Ogami, Kenneth Y., Power management architecture, method and configuration system.

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58. Luo, Jianfeng; Sinha, Subarnarekha; Su, Qing; Chiang, Charles C., Predicting IC manufacturing yield by considering both systematic and random intra-die process variations.

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59. Schultz David P. ; Hung Lawrence C. ; Goetting F. Erich, Programmable logic device with delay-locked loop.

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60. Boyle, Peter; Zamek, Iliya, Programmable logic device with performance variation compensation.

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61. Snyder, Warren, Programmable microcontroller architecture.

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62. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).

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63. Snyder, Warren; Mar, Monte, Programmable microcontroller architecture(mixed analog/digital).

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64. Thiagarajan, Eashwar; Sivadasan, Mohandas Palatholmana; Rohilla, Gajender; Kutz, Harold; Mar, Monte, Programmable sigma-delta analog-to-digital converter.

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65. Snyder, Warren; Maheshwari, Dinesh; Ogami, Kenneth; Hastings, Mark, Providing hardware independence to automate code generation of processing device firmware.

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66. Barcomb, Kevin J.; Huisman, Leendert M.; Olive, Mark F.; Quandt, Kevin C., Rapid fail analysis of embedded objects.

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67. Réblewski, Frédéric; LePape, Olivier V., Reconfigurable circuit with redundant reconfigurable cluster(s).

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68. Réblewski,Frédéric, Reconfigurable circuit with redundant reconfigurable cluster(s).

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69. Pleis, Matthew A.; Sullam, Bert; Lesher, Todd, Reconfigurable testing system and method.

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70. Pleis,Matthew A.; Sullam,Bert; Lesher,Todd, Reconfigurable testing system and method.

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71. Trimberger Stephen M., Reprogrammable instruction set accelerator.

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72. Trimberger Stephen M., Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page tab.

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73. Zhao, Jun; Yi, Yanhua; Ting, Eric, Scan chain systems and methods for programmable logic devices.

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74. Nemecek, Craig, Sleep and stall in an in-circuit emulation system.

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75. Trimberger,Stephen M., Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof.

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76. Ogami, Kenneth; Best, Andrew; Zhaksilikov, Marat, System and method for controlling a target device.

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77. Lee Tsu-Chang, System and method for determining acceptable logic cell locations and generating a legal location structure.

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78. Anderson, Douglas H.; Ogami, Kenneth Y., System and method for dynamically generating a configuration datasheet.

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79. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware.

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80. Baxter Michael A., System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization.

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81. Ogami, Kenneth Y.; Hood, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.

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82. Ogami, Kenneth Y.; Hood, III, Frederick R., System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit.

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83. Ma,Jing Hua; Zhang,Benhai, System for operating a programmable logic device having a defective region.

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84. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.

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85. Sullam, Bert; Snyder, Warren; Mohammed, Haneef, System level interconnect with programmable switching.

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86. Kamps,Bill, Systems and methods for geophysical imaging using amorphous computational processing.

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87. Kamps, Bill, Systems and methods for processing complex data sets.

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88. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, III, Frederick Redding, Techniques for generating microcontroller configuration information.

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89. Ogami, Kenneth Y.; Anderson, Doug; Pleis, Matthew; Hood, Rick, Techniques for generating microcontroller configuration information.

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90. Venkataraman, Garthik; Kutz, Harold; Mar, Monte, Temperature sensor with digital bandgap.

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91. Bartz, Manfred; Zhaksilikov, Marat; Anderson, Doug, User interface for efficiently browsing an electronic document using data-driven tabs.

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92. Landis, Lawrence David; Price, Richard, Using a single mask for various design configurations.

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93. Landis, Lawrence David; Price, Richard, Using a single mask for various design configurations.

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94. Trimberger,Stephen M., Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits.

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95. Trimberger, Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.

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96. Trimberger, Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.

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97. Trimberger,Stephen M., Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits.

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98. Jacobson, Neil G.; Corbett, John Damian, Verifying design isolation using bitstreams.

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99. Sivadasan, Mohandas Palatholmana; Rohilla, Gajendar, Voltage controlled oscillator delay cell and method.

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