$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Method for planarization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/463
출원번호 US-0188498 (1994-01-28)
발명자 / 주소
  • Paranjpe Ajit P. (Plano TX)
출원인 / 주소
  • Texas Instruments Incorporated (Dallas TX 02)
인용정보 피인용 횟수 : 85  인용 특허 : 0

초록

A method for planarization of the upper surface of a semiconductor wafer. A wafer with features formed thereon is loaded into the apparatus after having been coated with an interlevel dielectric. Thereafter, the wafer is subjected to suitably elevated temperature while a uniform elevated pressure is

대표청구항

A method for both global and local planarization of a surface of a semiconductor wafer having features formed thereon, the method comprising the steps of: a. filling the spaces between said features with an interlevel dielectric material to form a locally planarized surface; b. coating the wafer wit

이 특허를 인용한 특허 (85)

  1. Uchida, Takeshi; Matsuzawa, Jun; Hoshino, Tetsuya; Kamigata, Yasuo; Terazaki, Hiroki; Honma, Yoshio; Kondoh, Seiichi, Abrasive liquid for metal and method for polishing.
  2. Uchida, Takeshi; Matsuzawa, Jun; Hoshino, Tetsuya; Kamigata, Yasuo; Terazaki, Hiroki; Honma, Yoshio; Kondoh, Seiichi, Abrasive liquid for metal and method for polishing.
  3. Uchida, Takeshi; Matsuzawa, Jun; Hoshino, Tetsuya; Kamigata, Yasuo; Terazaki, Hiroki; Honma, Yoshio; Kondoh, Seiichi, Abrasive liquid for metal and method for polishing.
  4. Uchida, Takeshi; Matsuzawa, Jun; Hoshino, Tetsuya; Kamigata, Yasuo; Terazaki, Hiroki; Honma, Yoshio; Kondoh, Seiichi, Abrasive liquid for metal and method for polishing.
  5. Trent T. Ward, Apparatus and method for reducing removal forces for CMP pads.
  6. Ward Trent T., Apparatus and method for reducing removal forces for CMP pads.
  7. Ward, Trent T., Apparatus and method for reducing removal forces for CMP pads.
  8. Ward, Trent T., Apparatus and method for reducing removal forces for CMP pads.
  9. Ward, Trent T., Apparatus and method for reducing removal forces for CMP pads.
  10. Yokomizo,Kenji, Apparatus and method of securing a workpiece during high-pressure processing.
  11. McCutcheon, Jeremy; Lamb, III, James E., Automated process and apparatus for planarization of topographical surfaces.
  12. Conti Michael ; White Lawrence W. ; Tate William R. ; Able Stephen D., Check valve cartridge for fluid pump.
  13. McCutcheon, Jeremy W.; Brown, Robert D., Contact planarization apparatus.
  14. Endisch, Denis H.; Drage, James S., Contact planarization using nanoporous silica materials.
  15. Jones,William Dale, Control of fluid flow in the processing of an object with a fluid.
  16. Blalock Guy T. ; Stroupe Hugh E. ; Gordon Brian F., Deadhesion method and mechanism for wafer processing.
  17. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
  18. Blalock, Guy T.; Stroupe, Hugh E.; Gordon, Brian F., Deadhesion method and mechanism for wafer processing.
  19. Prybyla Judith Ann ; Taylor Gary Newton, Device fabrication involving planarization.
  20. Sreenivasan,Sidlgata V., Eliminating printability of sub-resolution defects in imprint lithography.
  21. Wang,David C.; Xu,Frank Y., Etching technique to planarize a multi-layer structure.
  22. Choi,Byung Jin; Meissl,Mario J.; Sreenivasan,Sidlagata V.; Watts,Michael P. C., Formation of discontinuous films during an imprint lithography process.
  23. Robinson Karl M., Formation of planar dielectric layers using liquid interfaces.
  24. Robinson, Karl M., Formation of planar dielectric layers using liquid interfaces.
  25. Sheydayi,Alexei; Sutton,Thomas, Gate valve for plus-atmospheric pressure semiconductor process vessels.
  26. Blalock Guy, Global planarization method and apparatus.
  27. Blalock Guy, Global planarization method and apparatus.
  28. Blalock Guy, Global planarization method and apparatus.
  29. Blalock, Guy, Global planarization method and apparatus.
  30. Jones, William D., High pressure fourier transform infrared cell.
  31. Biberger,Maximilian A.; Layman,Frederick Paul; Sutton,Thomas Robert, High pressure processing chamber for semiconductor substrate.
  32. Jones,William Dale, High-pressure processing chamber for a semiconductor wafer.
  33. Sreenivasan, Sidlgata V.; Choi, Byung-Jin, Imprinting of partial fields at the edge of the wafer.
  34. Chou,Stephen Y., Laser assisted direct imprint lithography.
  35. Chou,Stephen Y., Lithographic apparatus for molding ultrafine features.
  36. Givens John H., Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices.
  37. Chou, Stephen Y., Method and apparatus for high density nanostructures.
  38. Chou, Stephen Y., Method and apparatus for high density nanostructures.
  39. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Method and system for double-sided patterning of substrates.
  40. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  41. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  42. Blalock, Guy T.; Stroupe, Hugh E.; Carroll, Lynn J., Method for applying uniform pressurized film across wafer.
  43. Nakagawa,Hideo; Sasago,Masaru; Endo,Masayuki; Hirai,Yoshihiko, Method for fabricating semiconductor device.
  44. Takagi Mikio,JPX, Method for producing semiconductor device and production apparatus of semiconductor device.
  45. Ward,Trent T., Method for reducing removal forces for CMP pads.
  46. Beitel, Gerhard; Ahlstedt, Mattias; Hartner, Walter; Schindler, Günther; Kastner, Marcus; Weinrich, Volker, Method for removing structures.
  47. Sreenivasan, Sidlgata V.; McMackin, Ian M.; Melliar-Smith, Christopher Mark; Choi, Byung-Jin, Method of concurrently patterning a substrate having a plurality of fields and a plurality of alignment marks.
  48. LaBrake,Dwayne L., Method of controlling the critical dimension of structures formed on a substrate.
  49. Christopher David Dobson GB, Method of filling a recess.
  50. Sreenivasan,Sidlgata V., Method of forming a recessed structure employing a reverse tone process.
  51. Vidusek,David A.; Sreenivasan,Sidlgata V.; Wang,David C., Method of forming an in-situ recessed structure.
  52. Sreenivasan,Sidlgata V., Method of forming stepped structures employing imprint lithography.
  53. Chou, Stephen Y.; Yu, Zhaoning; Wu, Wei, Method of making an article comprising nanoscale patterns with reduced edge roughness.
  54. Calveley Peter Braden,NZX, Method of patterning a metal layer.
  55. Miller,Michael N.; Stacey,Nicholas A., Method of patterning surfaces while providing greater control of recess anisotropy.
  56. Matsuda Tetsuo (Poughkeepsie NY) Okumura Katsuya (Poughkeepsie NY), Method of planarizing a semiconductor workpiece surface.
  57. Sreenivasan, Sidlgata V.; Watts, Michael P. C., Method to arrange features on a substrate to replicate features having minimal dimensional variability.
  58. Marsh, Eugene P., Methods for planarization of non-planar surfaces in device fabrication.
  59. Sreenivasan, Sidlgata V., Pattern reversal employing thick residual layers.
  60. Sreenivasan, Sidlgata V.; Schumaker, Philip D., Patterning a plurality of fields on a substrate to compensate for differing evaporation times.
  61. Stacey,Nicholas A.; Sreenivasan,Sidlgata V.; Miller,Michael N., Patterning substrates employing multi-film layers defining etch-differential interfaces.
  62. Choi, Byung-Jin; Sreenivasan, Sidlgata V., Patterning substrates employing multiple chucks.
  63. Shih,Wu Sheng; Lamb, III,James E.; Minzey Snook,Juliet Ann; Daffron,Mark G., Planarization method for multi-layer lithography processing.
  64. Eugene P. Marsh, Planarization of non-planar surfaces in device fabrication.
  65. Marsh Eugene P., Planarization of non-planar surfaces in device fabrication.
  66. Doan Trung T. ; Blalock Guy T. ; Durcan Mark ; Meikle Scott G., Planarization process for semiconductor substrates.
  67. Doan, Trung T.; Blalock, Guy T.; Durcan, Mark; Meikle, Scott G., Planarization process for semiconductor substrates.
  68. Sreenivasan,Sidlgata V., Positive tone bi-layer imprint lithography method.
  69. Sreenivasan, Sidlgata V., Positive tone bi-layer method.
  70. Jeffrey P. Gambino ; William F. Landers, Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby.
  71. Sreenivasan,Sidlgata V.; Stacey,Nicholas A., Reverse tone patterning on surfaces having planarity perturbations.
  72. Schmid, Gerard M.; Stacey, Nicholas A; Resnick, Douglas J.; Voisin, Ronald D.; Myron, Lawrence J., Self-aligned process for fabricating imprint templates containing variously etched features.
  73. Bai, Dongshun; Shao, Xie; Fowler, Michelle; Tang, Tingji, Self-leveling planarization materials for microelectronic topography.
  74. Cathey David A. ; Durcan Mark, Semiconductor processing method using high pressure liquid media treatment.
  75. David A. Cathey ; Mark Durcan, Semiconductor processing method using high pressure liquid media treatment.
  76. Huang Yuan-Chang (Hsin-chu TWX), Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue.
  77. Sreenivasan, Sidlgata V.; Choi, Byung J.; Schumaker, Norman E.; Voisin, Ronald D.; Watts, Michael P. C.; Meissl, Mario J., Step and repeat imprint lithography processes.
  78. Moore,Scott E., System and method for filling openings in semiconductor products.
  79. Moore, Scott E., System for filling openings in semiconductor products.
  80. Moore, Scott E., System for filling openings in semiconductor products.
  81. Moore,Scott E., System for filling openings in semiconductor products.
  82. GanapathiSubramanian, Mahadevan; Choi, Byung-Jin; Miller, Michael N.; Stacey, Nicholas A., Technique for separating a mold from solidified imprinting material.
  83. Selinidis, Kosta S.; Choi, Byung-Jin; Schmid, Gerard M.; Thompson, Ecron D.; McMackin, Ian Matthew, Template having alignment marks formed of contrast material.
  84. Sreenivasan, Sidlgata V.; Schumaker, Philip D.; McMackin, Ian M., Tessellated patterns in imprint lithography.
  85. Jacobson,Gunilla; Yellowaga,Deborah, Treatment of a dielectric layer using supercritical CO.
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로