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Interconnect structure having improved metallization 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H06K-001/02
출원번호 US-0102027 (1993-08-03)
발명자 / 주소
  • Ahmad Umar M. U. (Both of Hopewell Junction NY) Kumar Ananda H. (Both of Hopewell Junction NY) Perfecto Eric D. (Wappingers Falls NY) Prasad Chandrika (Wappingers Falls NY) Purushothaman Sampath (Yor
출원인 / 주소
  • International Business Machines Corporation (Armonk NY 02)
인용정보 피인용 횟수 : 65  인용 특허 : 0

초록 ▼

An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electri

대표청구항 ▼

An electrical interconnect structure comprising: at least one electrically conducting feature on a surface of a substrate; a cap of electrically conducting metallization on the electrically conducting feature wherein said cap only partially covers said electrically conducting feature; and a layer of

이 특허를 인용한 특허 (65)

  1. Kang, Seung H.; Krebs, Roland P.; Steiner, Kurt George; Ayukawa, Michael C.; Merchant, Sailesh Mansinh, Aluminum pad power bus and signal routing for integrated circuit devices utilizing copper technology interconnect structures.
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  2. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Antifuse interconnect between two conducting layers of a printed circuit board.
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  3. Hansen Gregory Robert ; Matuszewski Scott William, Apparatus for attaching a surface mount component.
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  4. Yamada, Yasuyoshi, Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board.
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  6. Yu, Chen-Hua; Tseng, Horng-Huei, Bonding structure and fabrication thereof.
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  7. Bhansali Ameet, C4 substrate contact pad which has a layer of NI-B plating.
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  8. Leung, Andrew K W; McLellan, Neil; Low, Yip Seng, Circuit board with via trace connection and method of making the same.
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  10. Shih, Chao-Wen, Electrically connecting terminal structure of circuit board and manufacturing method thereof.
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  11. Hayama Masaaki,JPX ; Mohri Noboru,JPX ; Nakao Keiichi,JPX, Electronic part fabricated by intaglio printing.
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  13. Tee Onn Chong ; Chris Baldwin ; Chee-Yee Chung, Enhanced plated-through hole and via contact design.
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  14. Bhatt, Anilkumar C.; Markovich, Voya R.; Memis, Irving; Wilson, William E., Full additive process with filled plated through holes.
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  15. Anderson, James; Akerling, Gershon, High power chip scale package.
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  19. McCormack Mark Thomas ; Jiang Hunt Hang ; Massingill Thomas J. ; Beilin Solomon I., Method and structure of z-connected laminated substrate for high density electronic packaging.
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  21. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Method for making multilayered coaxial interconnect structure.
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  22. Anderson,James; Akerling,Gershon, Method for packaging integrated circuit chips.
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  23. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Method for supporting one or more electronic components.
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  24. Kwok Keung Paul Ho SG; Simon Chooi SG; Yi Xu SG; Yakub Aliyu SG; Mei Sheng Zhou SG; John Leonard Sudijono SG; Subhash Gupta SG; Sudipto Ranendra Roy SG, Method of application of conductive cap-layer in flip-chip, COB, and micro metal bonding.
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  25. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
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  26. Wu, Ming Ting; Larsen, III, Rulon J.; Kim, Young; Kim, Kieun; Cohen, Adam L.; Kumar, Ananda H.; Lockard, Michael S.; Smalley, Dennis R., Multi-layer, multi-material micro-scale and millimeter-scale devices with enhanced electrical and/or mechanical properties.
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  27. Nogami Takeshi ; Lopatin Sergey ; Pramanick Shekhar, Multi-layered coaxial interconnect structure.
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  28. Lan James J. D. ; Chiang Steve S. ; Wu Paul Y. F. ; Xie John Y., Multilayer board having insulating isolation rings.
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  29. Yamamoto Hiroshi,JPX ; Ohta Tomohiro,JPX ; Takeyasu Nobuyuki,JPX, Multilevel interconnect method of manufacturing.
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  30. Yamamoto Hiroshi (Chiba JPX) Ohta Tomohiro (Chiba JPX) Takeyasu Nobuyuki (Chiba JPX), Multilevel interconnect structure.
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  31. Rateiczak, Mitja; Schlarb, Andreas; Reul, Bernhard; Ziegler, Stefan, Pane having electrical connecting element.
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  32. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Personalization structure for semiconductor devices.
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  33. Lin,Mou Shiung; Lee,Jin Yuan, Post passivation structure for semiconductor chip or wafer.
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  34. Frankoski Edward Jay ; Memis Irving, Printed circuit boards for mounting a semiconductor integrated circuit die.
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  35. Lan James J. D. ; Chiang Steve S. ; Shepherd William H. ; Wu Paul Y. F., Programmable/reprogrammable structure using fuses and antifuses.
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  36. Geffken Robert Michael ; Motsiff William Thomas ; Uttecht Ronald R., Semi-conductor personalization structure and method.
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  37. Cheng, Hsu Ming, Space transformer having multi-layer pad structures.
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  38. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  39. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  40. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  41. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  42. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  43. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  44. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
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  45. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  46. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  47. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
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  48. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  49. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  50. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  51. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  52. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  53. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  54. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  55. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  56. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  57. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  58. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  59. Lin,Mou Shiung, Top layers of metal for high performance IC's.
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  60. Lin, Mou-Shiung; Chou, Chiu-Ming; Chou, Chien-Kang, Top layers of metal for integrated circuits.
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  61. Shepherd William H. ; Chiang Steve S. ; Xie John Y., Use of conductive particles in a nonconductive body as an integrated circuit antifuse.
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  62. Oprysko,Modest; Shan,Lei; Trewhella,Jeannine M., Via and via landing structures for smoothing transitions in multi-layer substrates.
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  63. Test, Howard R.; Amador, Gonzalo; Subido, Willmar E., Wire bonding process for copper-metallized integrated circuits.
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  64. Seshan, Krishna; Singh, Kuljeet, Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method.
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  65. Kobayashi, Toshio, Wiring board, method of manufacturing the same, and semiconductor device having wiring board.
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