이 특허를 인용한 특허 (36)

1. Leijten Nowak,Katarzyna, Configuration memory implementation for LUT-based reconfigurable logic architectures.

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2. Altaf K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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3. Altaf, K. Risa, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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4. K. Risa Altaf, Driver circuitry for programmable logic devices with hierarchical interconnection resources.

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5. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., FIFO in FPGA having logic elements that include cascadable shift registers.

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6. Bauer Trevor J. ; Young Steven P., FPGA architecture with deep look-up table RAMs.

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7. Bauer Trevor J. ; Young Steven P., FPGA architecture with dual-port deep look-up table RAMS.

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8. Bauer Trevor J. ; Young Steven P., FPGA architecture with wide function multiplexers.

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9. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA logic cell internal structure including pair of look-up tables.

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10. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector clock lines.

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11. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., FPGA structure having main, column and sector reset lines.

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12. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells.

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13. Furtek Frederick C. ; Mason Martin T. ; Luking Robert B., Field programmable gate array with distributed RAM and increased cell utilization.

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14. Ngai, Tony; Pedersen, Bruce; Shumarayev, Sergey; Schleicher, James; Huang, Wei-Jen; Hutton, Michael; Maruri, Victor; Patel, Rakesh; Kazarian, Peter J.; Leaver, Andrew; Mendel, David W.; Park, Jim, Interconnection and input/output resources for programmable logic integrated circuit devices.

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15. David W. Mendel ; Richard G. Cliff, Logic element for a programmable logic integrated circuit.

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16. Bauer Trevor J., Lookup tables which double as shift registers.

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17. Chapman, Kenneth D., Method and apparatus for de-spreading spread spectrum signals.

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18. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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19. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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20. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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21. Scheuermann, W. James, Method and system for reconfigurable channel coding.

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22. Ralph D. Wittig ; Sundararajarao Mohan ; Hamish T. Fallside, Method for implementing wide gates and tristate buffers using FPGA carry logic.

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23. Metzgen,Paul; Nancekievill,Dominic, Multiplexer configuration for programmable logic device.

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24. Selvidge Charles W. ; Agarwal Anant ; Babb Johnathan ; Dahl Matthew L., Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computat.

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25. Selvidge Charles W. (Charlestown MA) Agarwal Anant (Framingham MA) Babb Johnathan (Ringgold GA) Dahl Matthew L. (Marlboro MA), Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computat.

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26. Ng, Bee Yee; Phoon, Hee Kong; Ooi, Teik Hong; Oh, Guan Hoe, Power gated lookup table circuitry.

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27. Chandhoke, Sundeep, Programmable controller with multiple processors using a scanning architecture.

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28. Sueyoshi, Toshinori; Iida, Masahiro, Programmable logic circuit device having look up table enabling to reduce implementation area.

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29. Andy L. Lee ; Christopher F. Lane ; Bruce B. Pedersen, Programmable logic devices with enhanced multiplexing capabilities.

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30. Lee Andy L. ; Lane Christopher F. ; Pedersen Bruce B., Programmable logic devices with enhanced multiplexing capabilities.

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31. Lee Andy L. ; Lane Christopher F. ; Pedersen Bruce B., Programmable logic devices with enhanced multiplexing capabilities.

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32. Bauer Trevor J. ; Newgard Bruce A. ; Allaire William E. ; Young Steven P., Structure for optionally cascading shift registers.

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33. Chandhoke,Sundeep, System and method for automatically updating the memory map of a programmable logic controller to customized hardware.

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34. Tamba Nobuo,JPX ; Kusunoki Mitsugu,JPX ; Miyazaki Takeshi ; Masaki Akira,JPX ; Yamagiwa Akira,JPX, Variable logic circuit and semiconductor integrated circuit using the same.

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35. Agarwal Anant (Framingham MA) Babb Jonathan (Ringgold GA) Tessier Russell (Cambridge MA), Virtual interconnections for reconfigurable logic systems.

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36. Agarwal Anant ; Babb Jonathan ; Tessier Russell, Virtual interconnections for reconfigurable logic systems.

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