$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Decoded instruction cache architecture with each instruction field in multiple-instruction cache line directly connected 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/30
출원번호 US-0173136 (1993-12-22)
발명자 / 주소
  • Rustad Einar (Oslo NOX) Bakka Bjorn O. (Oslo NOX) Birkeli Inge (Oslo NOX) Orthe Nils A. (Finstadfordet NOX)
출원인 / 주소
  • Dolphin Interconnect Solutions AS (Oslo NOX 03)
인용정보 피인용 횟수 : 66  인용 특허 : 0

초록 ▼

A general purpose computer system is equipped with apparatus for enabling a processor to provide efficient execution of multiple instructions per clock cycle. The major feature is a decoded instruction cache with multiple instructions per cache line. During run time cache hits, the decode logic fill

대표청구항 ▼

In a general purpose computer having specialized functional units for parallel execution of instructions utilizing an instruction cache with one or more directories for parallel access to instructions issued to the functional units simultaneously, the instruction cache comprising: instruction cache

이 특허를 인용한 특허 (66)

  1. Kevin J. McGrath ; Michael T. Clark ; Scott A. White, Alternate fault handler.
    상세보기
  2. Mahalingaiah Rupaka ; Miller Paul K., Apparatus and method for detecting microbranches early.
    상세보기
  3. Mahalingaiah Rupaka ; Miller Paul K., Apparatus and method for detecting microbranches early.
    상세보기
  4. Mahalingaiah Rupaka ; Miller Paul K., Apparatus and method for detecting microbranches early.
    상세보기
  5. Fisher Joseph A. ; Faraboschi Paolo ; Emerson Paul G. ; Raje Prasad A., Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs.
    상세보기
  6. Dowling Eric M., Apparatus and method for program level parallelism in a VLIW processor.
    상세보기
  7. Eric M. Dowling, Apparatus and method for program level parallelism in a VLIW processor.
    상세보기
  8. Pickett James K. ; Tran Thang M., Apparatus for aligning instructions using predecoded shift amounts.
    상세보기
  9. Worrell Frank, Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended.
    상세보기
  10. Dujari Rajeev, Automatic cache synchronization.
    상세보기
  11. Zhang, Danpo; Cohen, Josh; Dujari, Rajeev; Ellerman, E. Castedo, Background cache synchronization.
    상세보기
  12. Tran Thang M., Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions.
    상세보기
  13. Luick David Arnold, Circuit arrangement and method of speculative instruction execution utilizing instruction history caching.
    상세보기
  14. Hampapuram Hari ; Lee Yen C. ; Ang Michael ; Jacobs Eino, Compiler generating swizzled instructions usable in a simplified cache layout.
    상세보기
  15. Takewa Hidehito,JPX ; Matsuo Shigeru,JPX ; Fujiwara Shinji,JPX ; Narita Masahisa,JPX, Data processor for processing a complex instruction by dividing it into executing units.
    상세보기
  16. Yeh Tse-Yu ; Poplingher Mircea ; Chen Wenliang ; Mulder Hans, Dynamic branch prediction for branch instructions with multiple targets.
    상세보기
  17. Dujari Rajeev, Dynamic network cache directories.
    상세보기
  18. Worrell Frank, Dynamically variable length CPU pipeline for efficiently executing two instruction sets.
    상세보기
  19. Pickett James K. ; Tran Thang M., Fetching instructions from an instruction cache using sequential way prediction.
    상세보기
  20. Leitner,Raimund; Panis,Christian, Fetching instructions to instruction buffer for simultaneous execution with long instruction sensing or buffer overwrite control.
    상세보기
  21. Pickett James K., Functional bit identifying a prefix byte via a particular state regardless of type of instruction.
    상세보기
  22. Mehra Vijay Krishna, Guard bits in a VLIW instruction control routing of operations to functional units allowing two issue slots to specify.
    상세보기
  23. Tran Thang ; Witt David B., High performance superscalar alignment unit.
    상세보기
  24. Tran Thang ; Witt David B., High performance superscalar alignment unit.
    상세보기
  25. Thang Tran ; David B. Witt, Instruction alignment unit for routing variable byte-length instructions.
    상세보기
  26. Sachs,Howard G.; Arya,Siamak, Instruction cache association crossbar switch.
    상세보기
  27. Howard G. Sachs ; Siamak Arya, Instruction cache associative crossbar switch.
    상세보기
  28. Sachs Howard G., Instruction cache associative crossbar switch system.
    상세보기
  29. Pickett James K. ; Tran Thang M., Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches.
    상세보기
  30. Lin, Shuaibin, Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions.
    상세보기
  31. Keller, James B.; Sharma, Puneet; Schakel, Keith R.; Matus, Francis M., Line predictor entry with location pointers and control information for corresponding instructions in a cache line.
    상세보기
  32. Worrell Frank ; Ekner Hartvig,DKX, Method and apparatus for allowing execution of both compressed instructions and decompressed instructions in a micropro.
    상세보기
  33. Gad S. Sheaffer, Method and apparatus for constructing a pre-scheduled instruction cache.
    상세보기
  34. Farber Yaron,ILX ; Sheaffer Gad,ILX ; Valentine Robert,ILX, Method and apparatus for merging binary translated basic blocks of instructions.
    상세보기
  35. Cook Thomas E. ; Liao Yu-Chung C. ; Sandon Peter A., Method and apparatus for performing multi-way branching using a hardware relational table.
    상세보기
  36. Tran Thang M., Method and apparatus for predecoding variable byte length instructions for fast scanning of instructions.
    상세보기
  37. Altman, Erik R.; Moreno, Jaime H.; Moudgill, Mayan, Method and apparatus for reducing encoding needs and ports to shared resources in a processor.
    상세보기
  38. Ebcioglu Kemal ; Kiefer Kenneth J. ; Luick David Arnold ; Silberman Gabriel Mauricio ; Winterfield Philip Braun, Method and apparatus to select the next instruction in a superscalar or a very long instruction word computer having N-way branching.
    상세보기
  39. Tremblay, Marc; Chaudhry, Shailender; Jacobson, Quinn A., Method and structure for explicit software control using scoreboard status information.
    상세보기
  40. Dujari,Rajeev, Method and system for directory balancing.
    상세보기
  41. McDonald Robert Greg, Method and system for fetching noncontiguous instructions in a single clock cycle.
    상세보기
  42. Yoshida Shoji,JPX ; Hotta Takashi,JPX ; Tanaka Shigeya,JPX, Method of controlling parallel processing at an instruction level and processor for realizing the method.
    상세보기
  43. Ussery Cary ; Levia Oz ; Ryan Raymond, Method of generating application specific integrated circuits using a programmable hardware architecture.
    상세보기
  44. Black Bryan P. (Austin TX) Denman Marvin A. (Austin TX), Method of operating a data processor with rapid address comparison for data forwarding.
    상세보기
  45. Thomas L. Drabenstott ; Gerald G. Pechanek ; Edwin F. Barry ; Charles W. Kurak, Jr., Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution.
    상세보기
  46. Kevin J. McGrath ; James K. Pickett, Microcode patch device and method for patching microcode using match registers and patch routines.
    상세보기
  47. Cai George Z. N. ; Shiell Jonathan H., Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer.
    상세보기
  48. Worrell Frank ; Ekner Hartvig,DKX, Microprocessor having register dependent immediate decompression.
    상세보기
  49. Dockser Kenneth A. (San Jose CA), Microprocessor system having instruction cache with reserved branch target section.
    상세보기
  50. Dujari Rajeev, Partial file caching and read range resume system and method.
    상세보기
  51. Bondi James O. ; Dutta Simonjit ; Nanda Ashwini K., Pipelined microprocessor with branch misprediction cache circuits, systems and methods.
    상세보기
  52. Ang Michael ; Jacobs Eino, Planar cache layout and instruction stream therefor.
    상세보기
  53. Sheaffer, Gad S., Pre-steering register renamed instructions to execution unit associated locations in instruction cache.
    상세보기
  54. Keller, James B.; Sharma, Puneet; Schakel, Keith R.; Matus, Francis M., Predictor miss decoder updating line predictor storing instruction fetch address and alignment information upon instruction decode termination condition.
    상세보기
  55. Mallick Soummya ; Patel Rajesh Bhikhubhai ; Jessani Romesh Mangho, Processor and method for executing a branch instruction and an associated target instruction utilizing a single instruc.
    상세보기
  56. Nguyen Le Trong ; Park Heonchul, Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the mi.
    상세보기
  57. Shen, Gene W.; Lie, Sean, Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects.
    상세보기
  58. Tran Thang M., Register file having multiple register storages for storing data from multiple data streams.
    상세보기
  59. Tran Thang M., Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions.
    상세보기
  60. Keller, James B.; Sharma, Puneet; Schakel, Keith R.; Matus, Francis M., Training line predictor for branch targets.
    상세보기
  61. Luick David A. ; Winterfield Philip B., VLIW architecture and method for expanding a parcel.
    상세보기
  62. Sachs, Howard G.; Arya, Siamak, VLIW processor and method therefor.
    상세보기
  63. Pickett James K., Variable byte-length instructions using state of function bit of second byte of plurality of instructions bytes as indicative of whether first byte is a prefix byte.
    상세보기
  64. Luick David Arnold, Very long instruction word (VLIW) computer having efficient instruction code format.
    상세보기
  65. Slavenburg Gerrit Ary ; Mehra Vijay K., Write control unit.
    상세보기
  66. Circello Joseph C. (Phoenix AZ) Schimke David J. (Phoenix AZ), Zero-cycle multi-state branch cache prediction data processing system and method thereof.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로