$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Semiconductor device and a method of manufacturing thereof 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-027/01
  • H01L-029/10
  • H01L-027/02
  • H01L-023/48
출원번호 US-0268877 (1994-06-30)
우선권정보 JP-0271727 (1990-10-09)
발명자 / 주소
  • Yamaguchi Yasuo (Hyogo JPX) Ajika Natsuo (Hyogo JPX) Yamano Tsuyoshi (Hyogo JPX)
출원인 / 주소
  • Mitsubishi Denki Kabushiki Kaisha (Tokyo JPX 03)
인용정보 피인용 횟수 : 72  인용 특허 : 0

초록 ▼

A semiconductor device of a field effect transistor having an SOI structure is formed as below. Using a gate electrode 20 as a mask, n type impurities are implanted into an SOI layer of p type to form additional source/drain regions of intermediate concentration. Then, a relatively thin sidewall spa

대표청구항 ▼

A semiconductor device comprising: a semiconductor layer formed on an insulator layer, a channel region of a first conductivity type formed in said semiconductor layer, first source/drain regions of a second conductivity type formed in said semiconductor layer adjacent to the left and right sides of

이 특허를 인용한 특허 (72)

  1. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Wristers Derick J., CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar fr.
    상세보기
  2. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Wristers Derick J., CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions.
    상세보기
  3. Cheng,Shui Ming, CMOS transistor with high drive current and low sheet resistance.
    상세보기
  4. Zhang, Hongyong; Takemura, Yasuhiko; Konuma, Toshimitsu; Ohnuma, Hideto; Yamaguchi, Naoaki; Suzawa, Hideomi; Uochi, Hideki, Display device.
    상세보기
  5. Tripsas Nicholas H., Dopant profile spreading for arsenic source/drain.
    상세보기
  6. Yamazaki Shunpei,JPX ; Takemura Yasuhiko,JPX, Electro-optical device incorporating a peripheral dual gate electrode TFT driver circuit.
    상세보기
  7. Yamane Hiroyuki (Anjo JPX) Higuchi Yasushi (Okazaki JPX) Katada Mitsutaka (Toyokawa JPX) Iwamori Noriyuki (Okazaki JPX) Kawaguchi Tsutomu (Nagoya JPX) Kuzuhara Takeshi (Nukata-gun JPX), Enhancement-type semiconductor having reduced leakage current.
    상세보기
  8. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Hause Fred N., Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon.
    상세보기
  9. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Wristers Derick J., Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions.
    상세보기
  10. Cheek Jon D. ; Wristers Derick J. ; Toprac Anthony J., Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant.
    상세보기
  11. Cheek Jon D. ; Wristers Derick J. ; Toprac Anthony J., Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant.
    상세보기
  12. Shimizu, Satoshi; Oda, Hidekazu, MIS transistor and manufacturing method thereof.
    상세보기
  13. Gardner Mark I. ; Hause Fred N. ; Fulford ; Jr. H. Jim, MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch.
    상세보기
  14. Wu Shye-Lin,TWX, MOSFETS structure with a recessed self-aligned silicide contact and an extended source/drain junction.
    상세보기
  15. Kim, Kyoung Hwan, Mask ROM devices of semiconductor devices and method of forming the same.
    상세보기
  16. Takemura,Yasuhiko; Zhang,Hongyong; Teramoto,Satoshi, Method for manufacturing semiconductor device having metal silicide.
    상세보기
  17. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  18. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  19. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  20. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  21. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  22. Yamazaki, Shunpei; Ohtani, Hisashi, Method of fabricating a semiconductor device.
    상세보기
  23. Yamazaki,Shunpei; Ohtani,Hisashi, Method of fabricating a semiconductor device.
    상세보기
  24. Yamazaki,Shunpei; Ohtani,Hisashi, Method of fabricating a semiconductor device.
    상세보기
  25. Yamazaki,Shunpei; Ohtani,Hisashi, Method of fabricating a semiconductor device.
    상세보기
  26. Takemura, Yasuhiko; Zhang, Hongyong; Teramoto, Satoshi, Method of manufacturing a semiconductor device.
    상세보기
  27. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
    상세보기
  28. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
    상세보기
  29. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
    상세보기
  30. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
    상세보기
  31. Yamazaki, Shunpei, Method of manufacturing a semiconductor device.
    상세보기
  32. Yamazaki, Shunpei, Method of manufacturing a semiconductor device having a gate electrode formed over a silicon oxide insulating layer.
    상세보기
  33. Yamazaki, Shunpei, Method of manufacturing a semiconductor device including thermal oxidation to form an insulating film.
    상세보기
  34. Yamazaki, Shunpei, Method of manufacturing semiconductor device having island-like single crystal semiconductor layer.
    상세보기
  35. Fulford ; Jr. H. Jim ; Gardner Mark I. ; Wristers Derick J., Multiple spacer formation/removal technique for forming a graded junction.
    상세보기
  36. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Nonvolatile memory and electronic apparatus.
    상세보기
  37. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
    상세보기
  38. Fukunaga,Takeshi, Process for production of SOI substrate and process for production of semiconductor device.
    상세보기
  39. Fukunaga, Takeshi, Process for production of SOI substrate and process for production of semiconductor device including the selective forming of porous layer.
    상세보기
  40. Yamazaki, Shunpei, Semiconductor device.
    상세보기
  41. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
    상세보기
  42. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
    상세보기
  43. Takemura, Yasuhiko; Teramoto, Satoshi, Semiconductor device and a method for manufacturing the same.
    상세보기
  44. Hiroyuki Yamane JP; Yasushi Higuchi JP; Mitsutaka Katada JP; Noriyuki Iwamori JP; Tsutomu Kawaguchi JP; Takeshi Kuzuhara JP, Semiconductor device and fabrication process thereof.
    상세보기
  45. Jung,Jin Hyo, Semiconductor device and manufacturing method thereof.
    상세보기
  46. Takemura, Yasuhiko; Zhang, Hongyong; Teramoto, Satoshi, Semiconductor device and method for forming the same.
    상세보기
  47. Takemura, Yasuhiko; Zhang, Hongyong; Teramoto, Satoshi, Semiconductor device and method for forming the same.
    상세보기
  48. Takemura, Yasuhiko; Zhang, Hongyong; Teramoto, Satoshi, Semiconductor device and method for forming the same.
    상세보기
  49. Tsunoda,Akira; Yamazaki,Shunpei; Koyama,Jun, Semiconductor device and method for manufacturing the same.
    상세보기
  50. Tsunoda,Akira; Yamazaki,Shunpei; Koyama,Jun, Semiconductor device and method for manufacturing the same.
    상세보기
  51. Zhang, Hongyong; Takemura, Yasuhiko; Konuma, Toshimitsu; Ohnuma, Hideto; Yamaguchi, Naoaki; Suzawa, Hideomi; Uochi, Hideki, Semiconductor device and method of manufacture thereof.
    상세보기
  52. Zhang, Hongyong; Takemura, Yasuhiko; Konuma, Toshimitsu; Ohnuma, Hideto; Yamaguchi, Naoaki; Suzawa, Hideomi; Uochi, Hideki, Semiconductor device and method of manufacture thereof.
    상세보기
  53. Zhang, Hongyong; Takemura, Yasuhiko; Konuma, Toshimitsu; Ohnuma, Hideto; Yamaguchi, Naoaki; Suzawa, Hideomi; Uochi, Hideki, Semiconductor device and method of manufacture thereof.
    상세보기
  54. Zhang,Hongyong; Takemura,Yasuhiko; Konuma,Toshimitsu; Ohnuma,Hideto; Yamaguchi,Naoaki; Suzawa,Hideomi; Uochi,Hideki, Semiconductor device and method of manufacture thereof.
    상세보기
  55. Ohtani, Hisashi; Takano, Tamae; Yamazaki, Shunpei, Semiconductor device and method of manufacturing the same.
    상세보기
  56. Sugawara Masahiro,JPX ; Hazama Katsuki,JPX, Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof.
    상세보기
  57. Sugawara Masahiro,JPX ; Hazama Katsuki,JPX, Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof.
    상세보기
  58. Yamazaki, Shunpei; Ohtani, Hisashi; Koyama, Jun; Fukunaga, Takeshi, Semiconductor device having buried oxide film.
    상세보기
  59. Gardner, Mark I; Fulford, H. Jim, Semiconductor device having large-area silicide layer and process of fabrication thereof.
    상세보기
  60. Ohuchi Kazuya,JPX ; Shibata Hideki,JPX, Semiconductor device having salicide layer.
    상세보기
  61. Kim Hyun-Sik,KRX ; Shin Heon-Jong,KRX, Semiconductor device having spacer and method of making same.
    상세보기
  62. Suzawa Hideomi,JPX ; Takemura Yasuhiko,JPX, Semiconductor integrated circuit and method of fabricating same.
    상세보기
  63. Suzawa, Hideomi; Takemura, Yasuhiko, Semiconductor integrated circuit and method of fabricating same.
    상세보기
  64. Suzawa, Hideomi; Takemura, Yasuhiko, Semiconductor integrated circuit and method of fabricating same.
    상세보기
  65. Suzawa, Hideomi; Takemura, Yasuhiko, Semiconductor integrated circuit and method of fabricating same.
    상세보기
  66. Suzawa,Hideomi; Takemura,Yasuhiko, Semiconductor integrated circuit and method of fabricating same.
    상세보기
  67. Kawaguchi Tsutomu,JPX ; Katada Mitsutaka,JPX, Semiconductor memory device having high-concentration region around electric-field moderating layer in substrate.
    상세보기
  68. Yamazaki, Shunpei; Koyama, Jun; Miyanaga, Akiharu; Fukunaga, Takeshi, Semiconductor thin film and method of manufacturing the same and semiconductor device and method of manufacturing the same.
    상세보기
  69. Qi Xiang ; Wei Long ; Ming-Ren Lin, Semiconductor-on-insulator transistor with recessed source and drain.
    상세보기
  70. Mehrotra,Manoj; Kirmse,Karen Hildegard Ralston; Siddiqui,Shirin, Slim spacer implementation to improve drive current.
    상세보기
  71. Yamazaki,Shunpei; Miyanaga,Akiharu; Koyama,Jun; Fukunaga,Takeshi, Static random access memory using thin film transistors.
    상세보기
  72. Yamazaki, Shunpei; Miyanaga, Akiharu; Koyama, Jun; Fukunaga, Takeshi, Thin film semiconductor device and its manufacturing method.
    상세보기

관련 콘텐츠

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로