이 특허를 인용한 특허 (76)

1. Tanwar, Kunaljeet, BEOL integration scheme for copper CMP to prevent dendrite formation.

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2. Hao, Ming-Yin; Yew, Tri-Rung; Chen, Coming; Hsieh, Tsong-Minn; Peng, Nai-Chen; Yeh, Jih-Cheng, Capacitor in an interconnect system and method of manufacturing thereof.

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3. Derryl D. J. Allman ; Brian Bystedt, Capacitor with multiple-component dielectric and method of fabricating same.

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4. Allman, Derryl D. J.; Mansour, Nabil; Saopraseuth, Ponce, Capacitor with stoichiometrically adjusted dielectric and method of fabricating same.

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5. Chang, Weng; Liu, Chung-Shi, Chemical mechanical polish planarizing method with pressure compensating layer.

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6. Brusic, Vlasta; Edelstein, Daniel C.; Feeney, Paul M.; Guthrie, William; Jaso, Mark; Kaufman, Frank B.; Lustig, Naftali; Roper, Peter; Rodbell, Kenneth; Thompson, David B., Chemical-mechanical planarization of metallurgy.

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7. Gambino Jeffrey P. ; Narayan Chandrasekhar ; Kirihata Toshiaki, Conductor-insulator-conductor structure.

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8. Ahn, Kie Y.; Forbes, Leonard, Copper technology for ULSI metallization.

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9. Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda, Dual damascene bond pad structure for lowering stress and allowing circuitry under pads.

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10. Trivedi, Jigish, Dual depth trench isolation.

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11. Trivedi, Jigish D., Dual depth trench isolation.

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12. Chen Ying-Ho,TWX ; Jang Syun-Ming,TWX, Elimination of copper line damages for damascene process.

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13. Gregory A. Johnson ; Kunal Taravade ; Gayle Miller, Encapsulated-metal vertical-interdigitated capacitor and damascene method of manufacturing same.

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14. Greco,Stephen E.; Standaert,Theodorus E., Forming of local and global wiring for semiconductor product.

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15. Chidambarrao, Dureseti; Greco, Stephen E.; Low, Kia S., IC having viabar interconnection and related method.

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16. Chidambarrao, Dureseti; Greco, Stephen E.; Low, Kia S., IC having viabar interconnection and related method.

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17. Eiles, Travis M.; Paniccia, Mario J., Integrated circuit device having an embedded heat slug.

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18. Eiles, Travis M.; Paniccia, Mario J., Integrated circuit device having an embedded heat slug.

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19. Harvey Ian, Integrated circuit device interconnection techniques.

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20. Merchant Sailesh M. ; Vitkavage Daniel J. ; Vitkavage Susan C., Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture therefor.

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21. Vitkavage Susan C. ; Vitkavage Daniel J. ; Merchant Sailesh M., Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof.

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22. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit having conductors of enhanced cross-sectional area.

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23. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Integrated circuit which uses a damascene process for producing staggered interconnect lines.

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24. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.

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25. Manning,Monte, Integrated circuitry and a semiconductor processing method of forming a series of conductive lines.

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26. Manning, Monte, Integrated circuitry conductive lines.

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27. Allman, Derryl D. J.; Fuchs, Kenneth, Interconnect-embedded metal-insulator-metal capacitor.

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28. Derryl D. J. Allman ; John Q. Walker ; Verne C. Hornback ; Todd A. Randazzo, Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same.

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29. Sergey D. Lopatin ; Shekhar Pramanick ; Dirk Brown, Manufacturing method for semiconductor metalization barrier.

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30. Pallinti, Jayanthi; Dunton, Samuel V.; Nagahara, Ronald J., Metal planarization system.

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31. Erb Darrell M. ; Avanzino Steven C. ; Wang Fei, Method and apparatus for improved planarity metallization by electroplating and CMP.

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32. Koo, Kyung-Bum, Method for forming an electrical interconnection providing improved surface morphology of tungsten.

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33. Koo,Kyung Bum, Method for forming an electrical interconnection providing improved surface morphology of tungsten.

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34. Liaw Jhon-Jhy,TWX ; Yang Ching-Yau,TWX, Method for forming local interconnect metal structures via the addition of a titanium nitride anti-reflective coating.

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35. Gayle W. Miller ; Kenneth P. Fuchs, Method of electrically connecting and isolating components with vertical elements extending between interconnect layers in an integrated circuit.

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36. Jang Syun-Ming,TWX, Method of enclosing copper conductor in a dual damascene process.

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37. Liu, Chi-Wen; Wang, Ying-Lang, Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure.

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38. Takewaki, Toshiyuki; Ueno, Kazuyoshi, Method of forming a semiconductor device featuring copper wiring layers of different widths having metal capping layers of different thicknesses formed thereon.

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39. Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Brennan William S. ; Hause Fred N. ; Dawson Robert ; Michael Mark W., Method of forming an integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer.

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40. Sun Shih-Wei,TWX ; Hsieh Wen-Yi,TWX ; Lur Water,TWX ; Wang Kun-Chih,TWX, Method of forming bonding pad.

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41. Park,Sang Kyun, Method of forming copper wiring in semiconductor device.

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42. Hidemitsu Aoki JP, Method of manufacturing a semiconductor device.

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43. Nagashima, Naoki, Method of manufacturing a semiconductor device.

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44. Toyoda, Hiroshi; Yano, Hiroyuki; Minamihaba, Gaku; Fukushima, Dai; Matsuda, Tetsuo; Kaneko, Hisashi, Method of manufacturing semiconductor device including two-step polishing operation for cap metal.

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45. Gupta Subhash,SGX ; Ho Paul Kwok Keung,SGX ; Zhou Mei Sheng,SGX ; Chockalingam Ramasamy,SGX, Method to avoid copper contamination during copper etching and CMP.

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46. Gupta Subhash,SGX ; Ho Kwok Keung Paul,SGX ; Zhou Mei-Sheng,SGX ; Chool Simon,SGX, Method to avoid copper contamination on the sidewall of a via or a dual damascene structure.

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47. Tsu Shih TW; Ying-Ho Chen TW; Jih-Churng Twu TW, Method to prevent copper CMP dishing.

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48. Wong Harianto,SGX, Method to prevent dishing in chemical mechanical polishing.

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49. Tsu Shih TW, Method to reduce capacitance for copper interconnect structures.

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50. Wu Zhiqiang ; Jiang Tongbi ; Akram Salman, Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly.

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51. Manning Monte, Methods of forming conductive lines.

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52. Yoo Bong-Young,KRX ; Choi Si-Young,KRX, Methods of forming electrical interconnects on semiconductor substrates.

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53. Graettinger,Thomas M.; Zahurak,John K.; Trapp,Shane J.; Figura,Thomas Arthur, Methods of forming openings into dielectric material.

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54. Beilin Solomon I. ; Lee Michael G. ; Chou William T. ; Moresco Larry Louis ; Wang Wen-chou Vincent, Methods of planarizing structures on wafers and substrates by polishing.

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55. Beilin, Solomon I.; Lee, Michael G.; Chou, William T.; Moresco, Larry Louis; Wang, Wen-chou Vincent, Methods of planarizing structures on wafers and substrates by polishing.

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56. Sailesh Chittipeddi ; William Thomas Cochran ; Yehuda Smooha, Process for forming a dual damascene bond pad structure over active circuitry.

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57. Bothra Subhas, Reliable aluminum interconnect via structures.

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58. Bothra Subhas, Reliable interconnect via structures and methods for making the same.

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59. Shue Shau-Lin,TWX ; Yu Chen-Hua,TWX, Self-passivation of copper damascene.

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60. Usami, Tatsuya, Semiconductor device and manufacturing method thereof.

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61. Usami,Tatsuya, Semiconductor device and manufacturing method thereof.

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62. Suminoe,Shinji; Nakanishi,Hiroyuki; Ishio,Toshiya; Iwazaki,Yoshihide; Mori,Katsunobu, Semiconductor device having a leading wiring layer.

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63. Suminoe,Shinji; Nakanishi,Hiroyuki; Ishio,Toshiya; Iwazaki,Yoshihide; Mori,Katsunobu, Semiconductor device having a leading wiring layer.

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64. Lee,Seong Soo, Semiconductor device having a metal wiring structure.

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65. Gardner Mark I. ; Kadosh Daniel, Semiconductor device having tapered conductive lines and fabrication thereof.

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66. Shunpei Yamazaki JP; Etsuko Fujimoto JP; Atsuo Isobe JP; Toru Takayama JP; Kunihiko Fukuchi JP, Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it.

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67. Yamazaki,Shunpei; Fujimoto,Etsuko; Isobe,Atsuo; Takayama,Toru; Fukuchi,Kunihiko, Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it.

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68. Yamazaki, Shunpei; Fujimoto, Etsuko; Isobe, Atsuo; Takayama, Toru; Fukuchi, Kunihiko, Semiconductor device with semiconductor circuit comprising semiconductor units, and method of fabricating it.

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69. Sinha, Nishant; Chopra, Dinesh, Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods.

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70. Sinha, Nishant; Chopra, Dinesh, Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods.

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71. Sinha,Nishant; Chopra,Dinesh, Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods.

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72. Koutny, Jr., William W. C., Smooth metal semiconductor surface and method for making the same.

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73. Koutny, Jr.,William W. C., Smooth metal semiconductor surface and method for making the same.

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74. Clampitt, Darwin A., Spacer patterned, high dielectric constant capacitor.

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75. Clampitt,Darwin A., Spacer patterned, high dielectric constant capacitor and methods for fabricating the same.

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76. Twu, Jih-Churng; Chen, Ying-Ho; Shih, Tsu; Jang, Syun-Ming, Use of low-high slurry flow to eliminate copper line damages.

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