이 특허를 인용한 특허 (33)

1. Bayerer, Reinhold, Bonded system with coated copper conductor.

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2. Oh,Steve Tchang Hun; Choi,Hong K.; Tsaur,Bor Yeu; Fan,John C. C., Bonding pad for gallium nitride-based light-emitting device.

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3. Oh,Tchang Hun; Choi,Hong K.; Fan,John C. C.; Narayan,Jagdish, Bonding pad for gallium nitride-based light-emitting devices.

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4. Chopra, Dinesh; Fishburn, Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.

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5. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.

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6. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.

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7. Chopra,Dinesh; Fishburn,Fred, Conductive connection forming methods, oxidation reducing methods, and integrated circuits formed thereby.

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8. Narayan, Jagdish, Domain epitaxy for thin film growth.

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9. Riou, Jean-Christophe; Peyrard, Michel; Bailly, Eric, Electronic module for a piece of vehicle-borne aeronautic equipment and a piece of aeronautic equipment for an aeronautic vehicle.

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10. Colgan Evan George ; Rodbell Kenneth Parker ; Totta Paul Anthony ; White James Francis, Interconnect structure using Al.sub.2 -Cu for an integrated circuit chip.

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11. Hess, Kevin J.; Lee, Chu-Chung, Localized alloying for improved bond reliability.

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12. Hess, Kevin J.; Lee, Chu-Chung, Localized alloying for improved bond reliability.

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13. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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14. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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15. Schoenfeld, Aaron; Ma, Manny K. F.; Kinsman, Larry D.; Brooks, J. Mike; Allen, Timothy J., Method and apparatus for coupling a semiconductor die to die terminals.

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16. Stierman, Roger J.; Moore, Thomas M.; Shinn, Gregory B., Method for reworking metal layers on integrated circuit bond pads.

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17. Stierman, Roger J.; Moore, Thomas M.; Shinn, Gregory B., Method for reworking metal layers on integrated circuit bond pads.

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18. Ball Michael B., Method of improving interconnect of semiconductor device by utilizing a flattened ball bond.

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19. Ball Michael B., Method of improving interconnect of semiconductor devices by using a flattened ball bond.

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20. Michael B. Ball, Method of improving interconnect of semiconductor devices by using a flattened ball bond.

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21. Ball Michael B., Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond.

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22. Ball, Michael B., Method of improving interconnect of semiconductor devices by utilizing a flattened ball bond.

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23. Hatano, Masaaki; Usui, Takamasa, Semiconductor device.

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24. Suzuki Kouichi,JPX ; Sato Sadanobu,JPX ; Yamashita Yumiko,JPX, Semiconductor device having metal alloy for electrodes.

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25. Kurihara, Toshimichi; Toda, Tetsu; Tsubaki, Shigeki, Semiconductor device with an improved bonding pad structure and method of bonding bonding wires to bonding pads.

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26. Miyaki, Yoshinori; Suzuki, Hiromichi; Kaneda, Tsuyoshi, Semiconductor integrated circuit device and method of manufacturing the same.

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27. Miyaki,Yoshinori; Suzuki,Hiromichi; Kaneda,Tsuyoshi, Semiconductor integrated circuit device and method of manufacturing the same.

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28. Miyaki,Yoshinori; Suzuki,Hiromichi; Kaneda,Tsuyoshi, Semiconductor integrated circuit device and method of manufacturing the same.

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29. Miyaki,Yoshinori; Suzuki,Hiromichi; Kaneda,Tsuyoshi, Semiconductor integrated circuit device and method of manufacturing the same.

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30. Chittipeddi, Sailesh; Merchant, Sailesh Mansinh, Wire bonding method for copper interconnects in semiconductor devices.

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31. Uno, Tomohiro; Terashima, Shinichi; Kimura, Keiichi; Yamada, Takashi; Nishibayashi, Akihito, Wire bonding structure and method for forming same.

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32. Huang, Wen Pin; Hsu, Cheng Tsung; Tseng, Cheng Lan; Hung, Chih Cheng; Chen, Yu Chi, Wirebonded semiconductor package.

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33. Lee, Ta-Chun, Wirebonded semiconductor package.

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