IPC분류정보
| 국가/구분 |
United States(US) Patent
등록
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| 국제특허분류(IPC7판) |
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| 출원번호 |
US-0142901
(1993-10-22)
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발명자
/ 주소 |
- Dobbelaere Ivo J. (Palo Alto CA)
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| 출원인 / 주소 |
- The Board of Trustees of the Leland Stanford Junior University (Stanford CA 02)
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| 인용정보 |
피인용 횟수 :
54 인용 특허 :
0 |
초록
▼
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, or in logic circuits, is disclosed. In one embodiment, a plurality of internally delayed logic circuits, each having a single network node, is connected to the intermediate nodes of a pr
A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, or in logic circuits, is disclosed. In one embodiment, a plurality of internally delayed logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. Each speed-up circuit monitors the logic level on the network node. When a circuit detects a substantial change in logic level, it temporarily enforces that change by connecting its network node to either the high or the low logic level. Thus, on each node, a low-impedance enhancement of the signal driving the node temporarily appears. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards the new level, and their speed-up circuits in turn temporarily enforce the new level. Thus, a forced high-to-low or low-to-high level change on a node quickly propagates to its connected nodes.
대표청구항
▼
In an integrated circuit, a bi-directional bus repeater, having a supply node, a ground node, first and second network nodes, and circuitry, said circuitry providing means to detect a first rising change exceeding a predetermined threshold from a low logic level towards a high logic level on said fi
In an integrated circuit, a bi-directional bus repeater, having a supply node, a ground node, first and second network nodes, and circuitry, said circuitry providing means to detect a first rising change exceeding a predetermined threshold from a low logic level towards a high logic level on said first network node, providing means to temporarily provide a low-impedance connection between said first network node and said supply node, as well as between said second network node and said supply node, when said first rising change occurs while a low logic level is present on said second network node, said circuitry providing means to detect a second rising change exceeding a predetermined threshold from a low logic level towards a high logic level on said second network node, providing means to temporarily provide a low-impedance connection between said first network node and said supply node, as well as between said second network node and said supply node, when said second rising change occurs while a low logic level is present on said first network node, said circuitry providing means to detect a first falling change exceeding a predetermined threshold from a high logic level towards a low logic level on said first network node, providing means to temporarily provide a low-impedance connection between said first network node and said ground node, as well as between said second network node and said ground node, when said first falling change occurs while a high logic level is present on said second network node, said circuitry providing means to detect a second falling change exceeding a predetermined threshold from a high logic level towards a low logic level on said second network node, providing means to temporarily provide a low-impedance connection between said first network node and said ground node, as well as between said second network node and said ground node, when said second falling change occurs while a high logic level is present on said first network node.
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