[특허]All digital on-the-fly time delay calibrator

All digital on-the-fly time delay calibrator 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03D-003/24
출원번호	US-0105079 (1993-08-11)
발명자 / 주소	Guo Bin (Fremont CA) Kubinec Jim (Reno CA) Gershon Eugen (Los Gatos CA)
출원인 / 주소	Advanced Micro Devices Inc. (Sunnyvale CA 02)
인용정보	피인용 횟수 : 53 인용 특허 : 0

초록 ▼

An on-chip digital servo scheme for providing continuous calibration of integrated circuit on-chip time delay devices to provide real-time regulation against various parameter or environmental changes, such as processing, temperature and power supply variations. The techniques are particularly useful for semiconductor delay lines comprised of a selectable number of identical unit delay circuits having the same propagation time. This scheme constantly monitors the delay changes in the unit delay elements and calibrates the delay line by comparing the delay against a stable, crystal controlled reference clock period to determine, in each instance, how many unit delay elements in the delay line is needed to effectively delay the amount of time to equal the reference clock period. A real time digital pointer number is generated and updated while the device is in operation. This pointer can be used to inform or update other delay or time bases on the same integrated circuit substrate which are constructed from the same type of unit delay cell and which may choose to use a different number of unit delay cells. Accordingly, this scheme can then be used for various delay regulation purposes in and all-digital circuit, such as clock multiplication, pulse width regulation, and other applications where accurate, regulated, digital command controlled delay or time bases are needed.

대표청구항 ▼

A circuit in a semiconductor integrated circuit for providing a signal which is accurately representative of propagation delay in circuits in said integrated circuit comprising: an input terminal, said input terminal for receiving a clock reference signal; a serially connected chain of unit delay cells including a first unit delay cell, said first unit delay cell being connected to said input terminal to launch said clock reference signal for propagation down said chain of unit delay cells, each cell having an input and output; a plurality of taps, each tap being connected to a said unit delay cell, said tap providing a signal representative of said unit delay cell output; a phase comparator array, said phase comparator array including a plurality of logic gates, where each said tap has a logic gate corresponding to said tap, and each said corresponding logic gate having a first input connected to said input terminal for receiving said clock reference and a second input connected to said corresponding tap, each said logic gate having an output signal; circuit means to periodically simultaneously sample and hold a binary representation of the output value of each said output signal of each said logic gate output, wherein said sample and hold circuit means has substantially identical threshold response to falling signals and to rising signals so that a threshold change which lowers the sensitivity to a transition of said output signal of a said logic gate from a one to a zero will have a matching decrease in the sensitivity to a transition of said output signal of a said logic gate from a zero to a one so that the time of occurrence of the midpoint between a falling/rising signal transition time and the next rising/failing signal transition time is substantially unchanged as a function of threshold changes; means to analyze said output signals of each said logic gate to determine the address of the tap where said logic gate output goes from 1 to 0 being the window low address, and the address of said tap where said logic gate output goes from 0 to 1 being the window high address; and means to determine the address of the tap at which the phase of said propagating clock reference signal, in operation, is closest to being exactly in phase with said clock reference signal applied to said input terminal, said tap being called the zero tap, said means to determine the address of said zero tap being coupled to said means to analyze said output signals of each said logic gate, said means to determine the address of said zero tap including means for providing an output signal representative of said address of said zero phase tap which said output signals is accurately representative of propagation delay in circuits in said integrated circuit.

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