이 특허를 인용한 특허 (204)

1. Reynolds Carl V. ; Neussendorfer Alex M. ; Kennedy Jeffrey K., Apparatus for restraining adhesive overflow in a multilayer substrate assembly during lamination.

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2. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Assembly of electronic components.

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3. Yamamura,Hideho, BGA type semiconductor device and electronic equipment using the same.

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4. Yamamura,Hideho, BGA type semiconductor device and electronic equipment using the same.

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5. Leonard E. Mess, Ball grid array (BGA) encapsulation mold.

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6. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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7. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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8. Mess Leonard E., Ball grid array (BGA) encapsulation mold.

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9. Pedder David John,GBX, Ball grid array arrangement.

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10. Yeh Yung I,TWX ; Chao Te Tsung,TWX ; Hung Ya Ping,TWX ; Fang Hui Chin,TWX, Ball grid array package.

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11. Selna Erich (Mountain View CA), Ball grid array package for a integrated circuit.

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12. Higashiguchi Yutaka,JPX, Ball grid array package having electrodes on peripheral side surfaces of a package board.

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13. Tamio Humphrey ; Salvador Salcido, Jr., Ball grid array package with supplemental electronic component.

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14. Nakashima Takashi (Kitakyushu JPX), Ball grid assembly type semiconductor device having a heat diffusion function and an electric and magnetic shielding fun.

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15. Nishiura Shinichi,JPX ; Mochida Tooru,JPX, Bonding wire loop shape for a semiconductor device.

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16. Hembree, David R., Carrier for cleaning sockets for semiconductor components having contact balls.

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17. Barrow Mike (5000 Beechwood Ct. El Dorado Hills CA 95762), Circuit pattern for a ball grid array integrated circuit package.

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18. Davis, Terry W.; Son, Sun Jin, Conformal shield on punch QFN semiconductor package.

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19. James M. Wark, Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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20. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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21. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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22. Wark James M., Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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23. Farnworth Warren M., Direct connect carrier for testing semiconductor dice and method of fabrication.

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24. Barrow Michael, Eclipse via in pad structure.

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25. Joiner, Bennett A.; Zhou, Yaping; Herberg, Ben W., Electromagnetic noise shielding in semiconductor packages using caged interconnect structures.

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26. Williams, Susan; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Electronic component with wire bonds in low modulus fill encapsulant.

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27. Appelt Bernd Karl-Heinz ; Bhatt Anilkumar Chinuprasad ; Fuller ; Jr. James W. ; Lauffer John Matthew ; Markovich Voya Rista ; Rudik William John ; Wilson William Earl, Electronic device packages having glass free non conductive layers.

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28. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Electronic device with wire bonds adhered between integrated circuits dies and printed circuit boards.

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29. Garbelli Francesco,ITX ; Oggioni Stefano,ITX, Electronic package with enhanced pad design.

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30. Horiba Yasuhiro,JPX ; Kohmura Toshimi,JPX, Electronic part mounting device.

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31. Mess, Leonard E., Encapsulation method in a molding machine for an electronic device.

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32. Yeo, Yong Kee; Khan, Navas O.K.; Iyer, Mahadevan K., Enhanced chip scale package for wire bond dies.

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33. Naito Toshiki,JPX ; Ouchi Kazuo,JPX, Film carrier and semiconductor device using the same.

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34. Dirks, Peter Adrianus Jacobus, Fine-pitch routing in a lead frame based system-in-package (SIP) device.

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35. Moden,Walter L., Flip-chip adaptor package for bare die.

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36. Moden,Walter L., Flip-chip adaptor package for bare die.

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37. Moden, Walter L., Grid array packages.

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38. Moden, Walter L., Grid array packages and assemblies including the same.

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39. Webster,Steven; Wu,Ying Cheng; Liu,Kun Hsieh; Hsu,Po Chih, IC chip package with isolated vias.

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40. Haba, Belgacem; Chau, Ellis; Zohni, Wael; Damberg, Philip; Crisp, Richard Dewitt, Impedance controlled packages with metal sheet or 2-layer RDL.

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41. Haba, Belgacem; Chau, Ellis; Zohni, Wael; Damberg, Philip; Crisp, Richard Dewitt, Impedance controlled packages with metal sheet or 2-layer rdl.

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42. Haba, Belgacem; Chau, Ellis; Zohni, Wael; Damberg, Philip; Crisp, Richard Dewitt, Impedence controlled packages with metal sheet or 2-layer RDL.

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43. Swan, Johanna M.; Mahajan, Ravi V.; Natarajan, Bala, Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.

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44. Swan, Johanna M.; Natarajan, Bala; Chiang, Chien; Atwood, Greg; Rao, Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.

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45. Swan,Johanna M.; Natarajan,Bala; Chiang,Chien; Atwood,Greg; Rao,Valluri R., Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme.

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46. Koushik Banerjee ; Robert J. Chroneos, Jr. ; Tom Mozdzen, Integrated circuit package.

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47. Banerjee Koushik ; Chroneos ; Jr. Robert J. ; Mozdzen Tom, Integrated circuit package which contains two in plane voltage busses and a wrap around conductive strip that connects a bond finger to one of the busses.

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48. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Integrated circuit support for low profile wire bond.

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49. Bolken, Todd O., Interposers for semiconductor die packages with standard ball grill array footprint.

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50. Ooigawa Kinya,JPX ; Yoshida Tayuru,JPX ; Nakagawa Naoki,JPX, Lead frame for ball grid array, semiconductor device having it, and process for producing it.

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51. Crisp, Richard Dewitt; Haba, Belgacem; Zohni, Wael, Lead structures with vertical offsets.

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52. Johari-Galle, Houri; Judy, Michael W., MEMS device with stress relief structures.

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53. Kaanta, Bradley C.; Jia, Kemiao, Mechanically isolated MEMS device.

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54. Haba, Belgacem; Chau, Ellis; Zohni, Wael; Crisp, Richard Dewitt, Metal can impedance control structure.

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55. Akram Salman ; Wood Alan G. ; Hembree David R. ; Farnworth Warren M., Method and apparatus for testing semiconductor dice.

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56. Akram, Salman; Wood, Alan G.; Hembree, David R.; Farnworth, Warren M., Method and apparatus for testing semiconductor dice.

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57. Bolken, Todd O., Method for assembling semiconductor die packages with standard ball grid array footprint.

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58. Bolken,Todd O., Method for assembling semiconductor die packages with standard ball grid array footprint.

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59. Fjelstad Joseph, Method for encapsulating a semiconductor package having apertures through a sacrificial layer and contact pads.

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60. Lee Shaw Wei ; Takiar Hem P. ; Drummond Fred, Method for forming a panel of packaged integrated circuits.

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61. Young-rae Cho KR; Wook-yeol Ryu KR; Sang-kyun Lee KR, Method for manufacturing semiconductor package containing cylindrical type bump grid array.

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62. Banerjee Koushik ; Chroneos ; Jr. Robert J. ; Mozdzen Tom, Method for plating a bond finger of an intergrated circuit package.

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63. Verma, Chetan; Aggarwal, Sumeet; Lye, Meng Kong, Method for reducing surface area of pad limited semiconductor die layout.

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64. Akram Salman ; Wood Alan G. ; Hembree David R. ; Farnworth Warren M., Method for testing semiconductor dice and chip scale packages.

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65. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Method of adhering wire bond loops to reduce loop height.

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66. Chung Long Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of applying encapsulant to wire bonds.

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67. Yow, Kai Yun; Eu, Poh Leng, Method of assembling pressure sensor device.

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68. Thompson, Sr., Curtis C., Method of attaching a device to a circuit board.

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69. Falcone Frank ; Lewis Alan ; Newbold John, Method of encapsulating a wire bonded die.

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70. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of encapsulating wire bonds.

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71. Ball,Michael B., Method of fabricating a multi-die semiconductor package assembly.

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72. Hyoudo Haruo,JPX ; Tani Takayuki,JPX ; Shibuya Takao,JPX, Method of fabricating semiconductor device.

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73. Hyoudo Haruo,JPX ; Tani Takayuki,JPX ; Shibuya Takao,JPX, Method of fabricating semiconductor device.

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74. Hyoudo, Haruo; Tani, Takayuki; Shibuya, Takao, Method of fabricating semiconductor device.

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75. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Method of forming low profile wire bonds between integrated circuits dies and printed circuit boards.

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76. Glenn, Thomas P.; Hollaway, Roy D.; Panczak, Anthony E., Method of making near chip size integrated circuit package.

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77. Sasaki, Takaaki, Method of manufacturing a semiconductor package having semiconductor decice mounted thereon and elongate opening through which electodes and patterns are connected.

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78. Peter Michael Frederick Collins, Method of manufacturing wire bond pad.

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79. Akram Salman (Boise ID) Wood Alan G. (Boise ID) Farnworth Warren M. (Nampa ID), Method of producing a single piece package for semiconductor die.

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80. Rogy, Reinhard; Zenz, Christian, Method of producing a transponder and a transponder.

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81. Rogy, Reinhard; Zenz, Christian, Method of producing a transponder and a transponder.

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82. Chun Heung Sop,KRX, Method of producing semiconductor package having solder balls.

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83. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of reducing wire bond profile height in integrated circuits mounted to circuit boards.

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84. Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai; Silverbrook, Kia, Method of wire bond encapsulation profiling.

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85. Silverbrook, Kia; Chung-Long-Shan, Laval; Tankongchumruskul, Kiangkai, Method of wire bonding an integrated circuit die and a printed circuit board.

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86. Leonard E. Mess, Methods for ball grid array (BGA) encapsulation mold.

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87. Fjelstad Joseph, Methods for manufacturing a semiconductor package having a sacrificial layer.

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88. Fjelstad, Joseph, Methods for manufacturing resistors using a sacrificial layer.

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89. Fjelstad, Joseph, Methods for manufacturing resistors using a sacrificial layer.

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90. Fjelstad,Joseph, Methods for manufacturing resistors using a sacrificial layer.

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91. Fjelstad,Joseph, Methods for manufacturing resistors using a sacrificial layer.

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92. Moden, Walter L., Methods for providing and using grid array packages.

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93. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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94. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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95. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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96. Wark, James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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97. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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98. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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99. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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100. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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101. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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102. Wark,James M., Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice.

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103. Fjelstad Joseph, Microelectronic assembly with conductive terminals having an exposed surface through a dielectric layer.

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104. Haba, Belgacem; Marcucci, Brian, Microelectronic assembly with impedance controlled wirebond and conductive reference element.

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105. Haba, Belgacem; Marcucci, Brian, Microelectronic assembly with impedance controlled wirebond and conductive reference element.

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106. Haba, Belgacem; Marcucci, Brian, Microelectronic assembly with impedance controlled wirebond and conductive reference element.

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107. Haba, Belgacem; Marcucci, Brian, Microelectronic assembly with impedance controlled wirebond and reference wirebond.

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108. Haba, Belgacem; Marcucci, Brian, Microelectronic assembly with impedance controlled wirebond and reference wirebond.

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109. Murugan, Rajen Manicon; Mi, Minhong; Morrison, Gary Paul; Chen, Jie; Rhyner, Kenneth Robert; Beddingfield, Stanley Craig; Gupta, Chittranjan Mohan; Trombley, Django Earl, Millimeter wave integrated circuit with ball grid array package including transmit and receive channels.

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110. Siang, Ng Kok; Loon, Wong Wai, Mixed wire bonding profile and pad-layout configurations in IC packaging processes for high-speed electronic devices.

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111. Liu, Yong, Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same.

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112. Jensen, Ronald James; Scheid, David, Multi-tiered integrated circuit package.

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113. Glenn Thomas P. ; Hollaway Roy D.,PHX ; Panczak Anthony E., Near chip size integrated circuit package.

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114. Chu Edwin (Cupertino CA) Lai Hu-Kong (San Jose CA), Output mapping of die pad bonds in a ball grid array.

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115. Harney, Kieran; Long, Lewis, Packaged microchip with isolation.

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116. Karpman, Maurice S., Packaged microchip with isolator having selected modulus of elasticity.

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117. Karpman,Maurice S.; Hablutzel,Nicole; Farrell,Peter W.; Judy,Michael W.; Felton,Lawrence E.; Long,Lewis, Packaged microchip with premolded-type package.

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118. Shawn M. O'Connor ; Mark Allen Gerber ; Jean Desiree Miller, Packaged semiconductor with multiple rows of bond pads and method therefor.

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119. Silverman, Lawrence H., Pocket mounted chip having microstrip line.

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120. Appelt, Bernd K.; Bhatt, Anilkumar C.; Fuller, Jr., James W.; Lauffer, John M.; Markovich, Voya R.; Rudik, William J.; Wilson, William E., Printed circuit boards for electronic device packages having glass free non-conductive layers and method of forming same.

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121. Nishiyama Tousaku,JPX, Printed wiring board and assembly of the same.

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122. Glenn Thomas P., RF shielded device.

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123. Takeda Shinji,JPX, Resin-sealed type ball grid array IC package and manufacturing method thereof.

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124. Hotta Yuji,JPX, Sealing label for sealing semiconductor element.

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125. Kanai,Tomonori; Kishimoto,Kiyoharu; Kikuchi,Yuji, Semiconductor device.

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126. Kohjiro, Iwamichi; Nunogawa, Yasuhiro; Kikuchi, Sakae; Kondo, Shizuo; Adachi, Tetsuaki; Kagaya, Osamu; Sekine, Kenji; Hase, Eiichi; Yamashita, Kiichi, Semiconductor device.

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127. Kohjiro, Iwamichi; Nunogawa, Yasuhiro; Kikuchi, Sakae; Kondo, Shizuo; Adachi, Tetsuaki; Kagaya, Osamu; Sekine, Kenji; Hase, Eiichi; Yamashita, Kiichi, Semiconductor device.

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128. Kohjiro, Iwamichi; Nunogawa, Yasuhiro; Kikuchi, Sakae; Kondo, Shizuo; Adachi, Tetsuaki; Kagaya, Osamu; Sekine, Kenji; Hase, Eiichi; Yamashita, Kiichi, Semiconductor device.

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129. Han, Yi Seul; Lee, Tae Yong; Ryu, Ji Yeon, Semiconductor device and method of manufacturing thereof.

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130. Yamashita Taturou,JPX ; Takenaka Masashi,JPX, Semiconductor device and semiconductor device unit having ball-grid-array type package structure.

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131. Naval, Herbert delos Santos; Sur, Noel A.; Soriano, John A., Semiconductor device having EMI shielding and method therefor.

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132. Berry, Christopher J.; Scanlan, Christopher M., Semiconductor device having RF shielding and method therefor.

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133. Berry,Christopher J.; Scanlan,Christopher M., Semiconductor device having RF shielding and method therefor.

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134. Olson, Timothy L.; Scanlan, Christopher M.; Berry, Christopher J., Semiconductor device having RF shielding and method therefor.

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135. Kozono Hiroyuki,JPX, Semiconductor device having a multiple-terminal integrated circuit formed on a circuit substrate.

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136. Lee, Beng Siong; Teh, Guat Kew; Wong, Wai Keong, Semiconductor device having die pads isolated from interconnect portion and method of assembling same.

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137. Torres Victor Manuel ; Srikantappa Ashok ; Sharma Laxminarayan, Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad place.

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138. Sharma Laxminarayan ; Carpenter Burton J., Semiconductor device having plated contacts and method thereof.

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139. Yamada Shigeru,JPX ; Kohara Youichi,JPX, Semiconductor device having two pluralities of electrode pads, pads of different pluralities having different widths and respective pads of different pluralities having an aligned transverse edge.

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140. Park, Sung Sun; Jun, Ik Su; Ahn, Ye Sul, Semiconductor device with electromagnetic interference shielding.

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141. Usui,Ryosuke; Mizuhara,Hideki; Igarashi,Yusuke; Kojima,Noriaki; Sakamoto,Noriaki, Semiconductor device, method for manufacturing same and thin plate interconnect line member.

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142. Sasaki, Takaaki, Semiconductor device, semiconductor package for use therein, and manufacturing method thereof.

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143. Sasaki, Takaaki, Semiconductor device, semiconductor package for use therein, and manufacturing method thereof.

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144. Sasaki, Takaaki, Semiconductor device, semiconductor package for use therein, and manufacturing method thereof.

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145. Sasaki,Takaaki, Semiconductor device, semiconductor package for use therein, and manufacturing method thereof.

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146. Sasaki,Takaaki, Semiconductor device, semiconductor package for use therein, and manufacturing method thereof.

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147. Castro, Abram M.; Gerber, Mark A., Semiconductor flip-chip system having oblong connectors and reduced trace pitches.

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148. Inagawa,Hideho, Semiconductor integrated circuit device.

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149. Sugahara Kenji,JPX, Semiconductor integrated circuit device having short signal paths to terminals and process of fabrication thereof.

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150. Haba, Belgacem, Semiconductor module with serial bus connection to multiple dies.

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151. Sasaki Takaaki,JPX, Semiconductor package.

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152. Chun Heung Sup,KRX, Semiconductor package and a method of manufacturing thereof.

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153. Torres Victor Manuel ; Sharma Laxminarayan ; Srikantappa Ashok, Semiconductor package bond post configuration.

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154. Fjelstad, Joseph, Semiconductor package having light sensitive chips.

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155. Fjelstad,Joseph, Semiconductor package having light sensitive chips.

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156. Wenzel, Robert J.; Harper, Peter R., Semiconductor package having optimized wire bond positioning.

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157. Kim Jin Sung,KRX, Semiconductor package substrate and ball grid array (BGA) semiconductor package using same.

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158. Hembree David R. ; Akram Salman ; Gochnour Derek ; Farnworth Warren M., Semiconductor package with wire bond protective member.

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159. Hembree David R. ; Akram Salman ; Gochnour Derek ; Farnworth Warren M., Semiconductor package with wire bond protective member.

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160. Fjelstad, Joseph, Semiconductor packages having light-sensitive chips.

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161. Tu, Hsiu-Wen; Hsin, Chung-Hsien; Chen, Jian-Ru, Sensor package structure.

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162. Tu, Hsiu-Wen; Hsin, Chung-Hsien; Chen, Jian-Ru, Sensor package structure.

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163. Chun, Jong Ok; Karim, Nozad; Chen, Richard; Selli, Giuseppe; Kelly, Michael, Shield lid interconnect package and method.

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164. Fuentes, Ruben; Miller, Jr., August Joseph, Shielded electronic component package and method.

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165. St. Amand, Roger D.; Karim, Nozad O.; Longo, Joseph M.; Smith, Lee J.; Darveaux, Robert F.; Chun, Jong Ok; Mao, Jingkun, Shielding for a semiconductor package.

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166. Palmer David W. ; Gassman Richard A. ; Chu Dahwey, Silicon ball grid array chip carrier.

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167. Akram Salman ; Wood Alan G. ; Farnworth Warren M., Single piece package for semiconductor die.

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168. Juneja Nitin ; Thurairajaratnam Aritharan, Single reference plane plastic ball grid array package.

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169. Nitin Juneja ; Aritharan Thurairajaratnam, Single reference plane plastic ball grid array package.

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170. Oh Sang Eon,KRX, Solder ball grid array carrier package with heat sink.

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171. Thompson ; Sr. Curtis C., Solder paste brick.

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172. Corisis, David J.; Brooks, Jerry M.; Moden, Walter L., Stackable ball grid array package.

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173. Moden, Walter L., Stackable semiconductor device assemblies.

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174. Poo, Chia Yong; Jeung, Boon Suan; Waf, Low Siu; Yu, Chan Min; Loo, Neo Yong; Kwang, Chua Swee, Stackable semiconductor package and wafer level fabrication method.

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175. Farnworth, Warren M.; Wood, Alan G.; Brooks, Mike, Stackable semiconductor package having conductive layer and insulating layers.

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176. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.

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177. Warren M. Farnworth ; Alan G. Wood ; Mike Brooks, Stackable semiconductor package having conductive layer and insulating layers and method of fabrication.

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178. Haba, Belgacem, Stacked multi-die packages with impedance control.

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179. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.

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180. Farnworth Warren M. ; Wood Alan G. ; Brooks Mike, Stacked semiconductor package and method of fabrication.

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181. Katti, Romney R.; Tucker, James L., Stacking arrangement for integration of multiple integrated circuits.

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182. Zhang, Xin; Judy, Michael W.; Molnar, George M.; Needham, Christopher; Jia, Kemiao, Stress isolation platform for MEMS devices.

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183. Zhang, Xin; Judy, Michael; Chau, Kevin H. L.; Kuan, Nelson; Spooner, Timothy; Paydenkar, Chetan; Farrell, Peter, Stress mitigation in packaged microchips.

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