초록 ▼

Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system－including a processor, a local bus, local bus controls, and a memory subsystem－are contained in a single system unit (e.g. a card); (2) devices are couple

Disclosed method and apparatus allow for balanced usage of resources in dual bus computing systems wherein: (1) principal resources of the system－including a processor, a local bus, local bus controls, and a memory subsystem－are contained in a single system unit (e.g. a card); (2) devices are coupled to the system unit and to each other through a device communications bus that is also accessible to the processor of the system unit; (3) the system processor is required to have principal access to the local bus, as a “System Bus Master”, for time critical functions such as memory refresh; and (4) the devices include one or more devices that are required to have controlling access to the resources of the system unit, and for that purpose are required to have controlling access to the local bus as Alternate Bus Master entities. The disclosed arrangement allows an Alternate Bus Master operating in a burst mode, in which several cycles of data transfer may occur consecutively, to have continuous access to the local bus after a single signal handshaking exchange with the local bus controls; subject to over-riding conditions which ensure timely accomplishment of the time critical functions controlled by the processor/System Bus Master. The over-riding conditions are detected by special logic that acts, when necessary, to interrupt Alternate Bus Master access to the local bus without affecting the state of connection between the respective Alternate Bus Master and the communications bus.

대표청구항 ▼

A method for efficiently managing data transfers in a computer system containing processor and memory subsystems, peripheral devices, and a dual bus structure; said dual bus structure including a local bus interconnecting said processor and memory subsystems, and a communications bus interconnecting

A method for efficiently managing data transfers in a computer system containing processor and memory subsystems, peripheral devices, and a dual bus structure; said dual bus structure including a local bus interconnecting said processor and memory subsystems, and a communications bus interconnecting said local bus and said peripheral devices; said processor subsystem exerting bus master control over said dual bus structure; said peripheral devices including at least one Alternate Bus Master bursting (ABMB) device adapted for operating as a bus master relative to said communications bus for conducting multiple cycles of burst data transfer activity over said buses during a single interval in which the respective ABMB device controls access to said communications bus; said method comprising: while said ABMB device is in control of said communications bus, and conducting multiple cycles of burst data transfer activity over both said communications bus and said local bus: (a) monitoring said system for occurrence of a predetermined condition; and, upon detection of said condition, (b) suspending said ABMB device\s access to said local bus to allow for said processor subsystem to perform a task relative to said memory subsystem, while permitting said ABMB device to retain control of said communications bus; and, upon completion of said task, (c) permitting said ABMB device to reacquire access to said local bus and continue with other said cycles of data transfer activity over both said buses; wherein said monitoring step comprises monitoring said system for occurrences of first and second priority conditions; said first condition being associated with a requirement for said processor subsystem to perform a time-critical task relative to said memory subsystem, and said second condition being associated with a requirement for said processor subsystem to perform a non-time-critical task relative to said memory subsystem; wherein said suspending step is applied at the end of a given cycle of data transfer activity by said ABMB device when a said first priority condition is first detected during said given cycle, and said suspending step is applied after a predetermined number of n cycles (n>1) of said data transfer activity following said given cycle when a said second priority condition is first detected during said given cycle and no first priority condition is detected in said given cycle; wherein access of said ABMB device to said local bus requires performance of a predetermined handshake procedure between parts of said processor subsystem controlling access to said dual bus structure, each performance of said handshaking procedure imposing a predetermined minimal delay on the respective access of said ABMB device to said local bus; and wherein: when said cycles of data transfer activity by said ABMB device are suspended due to detection of a said first priority condition during a said given cycle, performance of a single instance of said handshaking procedure is distributed over all cycles of data transfer activity prior to the suspension, including said given cycle, and performance of said handshaking procedure is repeated and distributed over cycles of data transfer activity which resume after the suspension ends; and when said cycles of data transfer activity are suspended due to detection of a said second priority condition in said given cycle, performance of a single instance of said handshake procedure is distributed over all cycles of data transfer activity preceding the suspension, including said given cycle and said n cycles following said given cycle, and performance of said handshake procedure is repeated and distributed over any cycles of data transfer activity which resume after the suspension ends.