이 특허를 인용한 특허 (154)

1. Trezza, John, Back-to-front via process.

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2. Andricacos Panayotis Constantinou ; Datta Madhav ; Horkans Wilma Jean ; Kang Sung Kwon ; Kwietniak Keith Thomas, Barrier layers for electroplated SnPb eutectic solder joints.

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3. Kuo, Wen-Chang; Lin, Chia-Fu; Pan, Sheng-Liang; Wang, Szu-Yao; Chu, Cheng-Yu, Bump reflow method by inert gas plasma.

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4. Chen, Guan-Yu; Lin, Yu-Wei; Tseng, Yu-Jen; Kuo, Tin-Hao; Chen, Chen-Shien, Bump structure and method of forming same.

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5. Chen, Guan-Yu; Lin, Yu-Wei; Tseng, Yu-Jen; Kuo, Tin-Hao; Chen, Chen-Shien, Bump structure and method of forming same.

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6. Yu, Chen-Hua; Chen, Chen-Shien, Bump-on-trace interconnect.

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7. Yu, Chen-Hua; Chen, Chen-Shien, Bump-on-trace interconnect having varying widths and methods of forming same.

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8. Trezza, John, Chip capacitive coupling.

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9. Trezza, John, Chip capacitive coupling.

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10. Trezza, John; Callahan, John; Dudoff, Gregory, Chip connector.

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11. Trezza, John, Chip spanning connection.

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12. Trezza, John, Chip-based thermo-stack.

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13. Trezza, John, Chip-based thermo-stack.

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14. Trezza, John, Coaxial through chip connection.

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15. Akram Salman, Conductive bumps on die for flip chip application.

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16. Lin, Yen-Liang; Tseng, Yu-Jen; Huang, Chang-Chia; Kuo, Tin-Hao; Chen, Chen-Shien, Conductive contacts having varying widths and method of manufacturing same.

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17. Lin, Yen-Liang; Tseng, Yu-Jen; Huang, Chang-Chia; Kuo, Tin-Hao; Chen, Chen-Shien, Conductive contacts having varying widths and method of manufacturing same.

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18. Lin, Yen-Liang; Tseng, Yu-Jen; Huang, Chang-Chia; Kuo, Tin-Hao; Chen, Chen-Shien, Conductive contacts having varying widths and method of manufacturing same.

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19. Kuo, Tin-Hao; Chen, Chen-Shien; Lii, Mirng-Ji; Yu, Chen-Hua; Wu, Sheng-Yu; Chuang, Yao-Chun, Conical-shaped or tier-shaped pillar connections.

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20. Kuo, Tin-Hao; Chen, Chen-Shien; Lii, Mirng-Ji; Yu, Chen-Hua; Wu, Sheng-Yu; Chuang, Yao-Chun, Conical-shaped or tier-shaped pillar connections.

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21. Trezza, John; Callahan, John; Dudoff, Gregory, Contact-based encapsulation.

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22. Akram, Salman, Copper interconnect.

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23. Akram,Salman, Copper interconnect.

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24. Akram,Salman, Copper interconnect.

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25. Akram,Salman, Copper interconnect for semiconductor device.

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26. Datta, Madhav; Emory, Dave; Joshi, Subhash M.; Menezes, Susanne; Suh, Doowon, Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same.

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27. Dubin, Valery M.; Balakrishnan, Sridhar; Bohr, Mark, Designs and methods for conductive bumps.

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28. Dubin, Valery M.; Balakrishnan, Sridhar; Bohr, Mark, Designs and methods for conductive bumps.

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29. Dalal Hormazdyar Minocher ; Fallon Kenneth Michael, Direct chip attach circuit card.

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30. Trezza, John, Electrically conductive interconnect system and method.

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31. Trezza, John; Callahan, John; Dudoff, Gregory, Electronic chip contact structure.

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32. Ohtsuki, Tomonari; Yamazaki, Yasue, Electronic component and process for manufacturing the same.

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33. Wang, Jian; Yu, Gang, Electronic device including conductive members between a first workpiece and second workpiece.

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34. Jan, Jong Rong; Lu, Tsai Hua; Chiu, Sao Ling; Kung, Ling Chen, Electronic devices including offset conductive bumps.

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35. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods.

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36. Rinne, Glenn A.; Mis, J. Daniel, Electronic structures including barrier layers defining lips.

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37. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers.

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38. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Electronic structures including conductive shunt layers.

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39. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Flip chip interconnections on electronic modules.

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40. Aoki, Toyohiro; Horibe, Akihiro; Mori, Hiroyuki; Orii, Yasumitsu; Toriyama, Kazushige; Yang, Ting-Li, Forming a solder joint between metal layers.

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41. Aoki, Toyohiro; Horibe, Akihiro; Mori, Hiroyuki; Orii, Yasumitsu; Toriyama, Kazushige; Yang, Ting-Li, Forming a solder joint between metal layers.

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42. Trezza, John, Front-end processed wafer having through-chip connections.

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43. Akamatsu, Toshiya; Karasawa, Kazuaki; Nakanishi, Teru; Shimizu, Kozo, Integrated electronic device having flip-chip connection with circuit board and fabrication method thereof.

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44. Mitchell Douglas G. ; Carney Francis J. ; Woolsey Eric J., Interconnect system and method of fabrication.

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45. Lin, Yu-Wei; Wu, Sheng-Yu; Tseng, Yu-Jen; Kuo, Tin-Hao; Chen, Chen-Shien, Interconnection structure and method of forming same.

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46. Trezza, John, Inverse chip connector.

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47. Trezza, John, Inverse chip connector.

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48. Trezza, John, Isolating chip-to-chip contact.

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49. Trezza, John, Isolating chip-to-chip contact.

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50. Rinne,Glenn A.; Nair,Krishna K., Low temperature methods of bonding components and related structures.

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51. Milewski, Joseph M.; Woychik, Charles G., Low temperature solder chip attach structure.

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52. Milewski,Joseph M.; Woychik,Charles G., Low temperature solder chip attach structure and process to produce a high temperature interconnection.

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53. Evans Michael D. ; Goss James D. ; Curhan Jeffrey A. ; Vinciarelli Patrizio, Making a connection between a component and a circuit board.

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54. Farnworth, Warren M., Mask repattern process.

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55. Farnworth, Warren M., Mask repattern process.

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56. Wang, Weifan; Lin, Yi-Shen; Creasy, Jr., Larry D., Metallized film-over-foam contacts.

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57. Iacoponi, John A., Method and apparatus for forming an under bump metallurgy layer.

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58. Akram, Salman, Method and semiconductor device having copper interconnect for bonding.

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59. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.

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60. Sidhwa, Ardeshir J., Method and structure of a thick metal layer using multiple deposition chambers.

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61. Liu, Kuo-Chuan; Lee, Michael G., Method and system for joining and an ultra-high density interconnect.

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62. Lau James Chung-Kei ; Pilkington Geoffrey, Method for attaching an integrated circuit chip to a substrate and an integrated circuit chip useful therein.

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63. Munroe Robert A. ; Greer Stuart E., Method for forming interconnect bumps on a semiconductor die.

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64. Shiu,Hei Ming; Chau,On Lok; Lai,Gor Amie, Method for forming multi-layer bumps on a substrate.

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65. Shiu,Hei Ming; Chau,On Lok; Lai,Gor Amie, Method for forming multi-layer bumps on a substrate.

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66. Greer Stuart E. (Austin TX) Dietz Joel P. (Austin TX) Sparkman Aubrey K. (Austin TX), Method for testing and burning-in a semiconductor wafer.

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67. Kenneth Kaskoun DE; Erik Jung DE; Werner Budweiser DE, Method for transfering solder to a device and/or testing the device.

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68. Devin Robert Sheridan ; Larry J. Larsen ; Martie D. Knauss, Method of forming a semiconductor device having conductive bumps without using gold.

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69. Akram Salman, Method of forming conductive bumps on die for flip chip applications.

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70. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Method of forming interconnections on electronic modules.

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71. Shangguan Dongkai ; Paruchuri Mohan ; Achari Achyuta, Method of forming interconnections on electronic modules.

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72. Barr, Alexander L.; Venkatesan, Suresh; Clegg, David B.; Cole, Rebecca G.; Adetutu, Olubunmi; Greer, Stuart E.; Anthony, Brian G.; Venkatraman, Ramnath; Braeckelmann, Gregor; Reber, Douglas M.; Crown, Method of forming semiconductor device including interconnect barrier layers.

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73. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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74. Akram, Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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75. Akram,Salman, Method of improving copper interconnects of semiconductor devices for bonding.

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76. Kubota, Takashi; Kitajima, Masayuki; Yamakami, Takatoyo; Kira, Hidehiko, Method of mounting semiconductor element, and semiconductor device.

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77. Higdon William David ; Stepniak Frank ; Yeh Shing, Method of solder bumping a circuit component.

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78. Chen, Yen-Ming; Lin, Chia-Fu; Hsu, Shun-Liang; Ching, Kai-Ming; Lee, Hsin-Hui; Su, Chao-Yuan; Chen, Li-Chih, Method to improve bump reliability for flip chip device.

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79. Jensen, David G., Methods employing elevated temperatures to enhance quality control in microelectronic component manufacture.

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80. Mis Joseph Daniel, Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structu.

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81. Rinne,Glenn A.; Mis,J. Daniel, Methods of forming bumps using barrier layers as etch masks.

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82. Nair, Krishna K.; Rinne, Glenn A.; Batchelor, William E., Methods of forming electronic structures including conductive shunt layers and related structures.

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83. Nair,Krishna K.; Rinne,Glenn A.; Batchelor,William E., Methods of forming electronic structures including conductive shunt layers and related structures.

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84. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Methods of forming lead free solder bumps.

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85. Rinne, Glenn A., Methods of forming metal layers using multi-layer lift-off patterns.

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86. Mis,J. Daniel, Methods of forming solder bumps on exposed metal pads.

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87. Jan,Jong Rong; Lu,Tsai Hua; Chiu,Sao Ling; Kung,Ling Chen, Methods of selectively bumping integrated circuit substrates and related structures.

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88. Farnworth, Warren M.; Lake, Rick C.; Hiatt, William M., Microfeature workpieces having alloyed conductive structures, and associated methods.

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89. Farnworth, Warren M.; Lake, Rick C.; Hiatt, William M., Microfeature workpieces having alloyed conductive structures, and associated methods.

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90. Farnworth, Warren M.; Lake, Rickie C.; Hiatt, William M., Microfeature workpieces having alloyed conductive structures, and associated methods.

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91. Borthakur, Swarnal, Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods.

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92. Batchelor, William E.; Rinne, Glenn A., Non-Circular via holes for bumping pads and related structures.

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93. Rinne,Glenn A., Optical structures including liquid bumps and related methods.

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94. Leader ; III Charles C. ; Dearborn David D. ; Mitra Shantanu, Packaging system for field effects transistors.

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95. Kanda,Atsushi, Pad structures including insulating layers having a tapered surface.

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96. Trezza, John; Callahan, John; Dudoff, Gregory, Patterned contact.

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97. Trezza, John; Frushour, Ross, Pin-type chip tooling.

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98. Trezza, John, Plated pillar package formation.

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99. Galloway Terry R., Plating process for fine pitch die in wafer form.

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100. Trezza, John; Callahan, John; Dudoff, Gregory, Post & penetration interconnection.

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101. Trezza, John, Post-attachment chip-to-chip connection.

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102. Trezza, John, Process for chip capacitive coupling.

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103. Mangold Rick Lee ; Lance ; Jr. James George, Process for fabricating a solder bump for a flip chip integrated circuit.

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104. Wang, Jian; Yu, Gang, Process for fabricating and repairing an electronic device.

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105. Tong, Ho-Ming; Lee, Chun-Chi; Fang, Jen-Kuang; Huang, Min-Lung; Chen, Jau-Shoung; Su, Ching-Huei; Weng, Chao-Fu; Lee, Yung-Chi; Chou, Yu-Chen; Wu, Tsung-Hua; Tao, Su, Process for fabricating wafer bumps.

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106. Liu, Cheng-Yi; Wang, Shen-Jie; Kao, Cheng-Heng, Process of fabricating flip chip interconnection structure.

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107. Hormazdyar M. Dalal ; Gene Joseph Gaudenzi ; Rebecca Y. Gorrell ; Mark A. Takacs ; Kenneth J. Travis, Jr., Process of forming a capacitor with multi-level interconnection technology.

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108. Milewski Joseph M. ; Woychik Charles G., Process to produce a high temperature interconnection.

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109. Trezza, John, Processed wafer via.

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110. Trezza, John, Processed wafer via.

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111. Trezza, John; Callahan, John; Dudoff, Gregory, Profiled contact.

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112. Trezza, John, Redundant optical device array.

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113. Trezza, John, Remote chip attachment.

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114. Trezza, John, Remote chip attachment.

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115. Trezza, John; Frushour, Ross, Rigid-backed, membrane-based chip tooling.

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116. Misra, Abhay; Trezza, John, Routingless chip architecture.

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117. LaFontaine ; Jr. William Rena ; Mescher Paul Allen ; Woychik Charles Gerard, Semiconductor chip package having chip-to-carrier mechanical/electrical connection formed via solid state diffusion.

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118. Kuwabara, Keiji; Hanaoka, Terunao; Ito, Haruki, Semiconductor chip with plural resin layers on a surface thereof and method of manufacturing same.

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119. Otremba, Ralf, Semiconductor device.

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120. Yano, Takakazu; Morokawa, Shigeru; Masuda, Takashi; Watanabe, Makoto; Kikuchi, Masayoshi, Semiconductor device.

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121. Stuart E. Greer, Semiconductor device and a process for forming the semiconductor device.

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122. Sang-Don Yi KR; Byung-Soo Kim KR; Chang-Hun Lee KR; Soo-Cheol Lee KR, Semiconductor device and fabricating method therefor.

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123. Sang-Don Yi KR; Byung-Soo Kim KR; Chang-Hun Lee KR; Soo-Cheol Lee KR, Semiconductor device and fabricating method therefor.

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124. Greer, Stuart E., Semiconductor device and method of formation.

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125. Hanaoka, Terunao; Ito, Haruki; Nozawa, Kazuhiko, Semiconductor device and method of manufacture thereof, circuit board, and electronic instrument.

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126. Kuo, Chen-Cheng; Liu, Tzuan-Horng; Chen, Chen-Shien, Semiconductor device having conductive pads and a method of manufacturing the same.

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127. Kuo, Chen-Cheng; Liu, Tzuan-Horng; Chen, Chen-Shien, Semiconductor device having conductive pads and a method of manufacturing the same.

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128. Akram, Salman, Semiconductor device having copper interconnect for bonding.

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129. Masumoto, Mutsumi, Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles.

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130. Tatsumi,Kohei; Shimokawa,Kenji; Hashino,Eiji, Semiconductor device provided with low melting point metal bumps.

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131. Tago, Masamoto; Nishiyama, Tomohiro; Tao, Tetuya; Mikagi, Kaoru, Semiconductor device, manufacturing method and apparatus for the same.

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132. Tago, Masamoto; Nishiyama, Tomohiro; Tao, Tetuya; Mikagi, Kaoru, Semiconductor device, manufacturing method and apparatus for the same.

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133. Ohnishi, Yuya, Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device.

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134. Tseng, Yu-Jen; Lin, Yen-Liang; Kuo, Tin-Hao; Chen, Chen-Shien; Lii, Mirng-Ji, Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices.

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135. Tseng, Yu-Jen; Lin, Yen-Liang; Kuo, Tin-Hao; Chen, Chen-Shien; Lii, Mirng-Ji, Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices.

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136. Trezza, John, Side stacking apparatus and method.

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137. Mis Joseph Daniel ; Adema Gretchen Maerker ; Kellam Mark D. ; Rogers W. Boyd, Solder bump fabrication methods and structures including a titanium barrier layer.

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138. Sarma Dwadasi Hare Rama ; Paszkiet Christine Ann ; Orem James Catlin ; Needes Christopher Roderick, Solder process for enhancing reliability of multilayer hybrid circuits.

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139. Mis, J. Daniel; Adema, Gretchen; Bumgarner, Susan; Chilukuri, Pooja; Rinne, Christine; Rinne, Glenn, Solder structures including barrier layers with nickel and/or copper.

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140. Chan,Chingho Philip; Xiao,Guowei David, Stencil mask design method and under bump metallurgy for C4 solder bump.

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141. Sakai Tadahiko,JPX ; Sakemi Shoji,JPX ; Nishinaka Teruaki,JPX, Structure of electronic parts and method of soldering electronic parts to substrate.

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142. Tsai, Pei-Chun; Tseng, Yu-Jen; Kuo, Tin-Hao; Chen, Chen-Shien, Structures having a tapering curved profile and methods of making same.

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143. Shen, Wen-Wei; Shih, Ying-Ching; Chen, Chen-Shien; Chen, Ming-Fa, Substrate interconnections having different sizes.

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144. Shen, Wen-Wei; Shih, Ying-Ching; Chen, Chen-Shien; Chen, Ming-Fa, Substrate interconnections having different sizes.

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145. Jensen, David G., Systems employing elevated temperatures to enhance quality control in microelectronic component manufacture.

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146. Trezza, John, Thermally balanced via.

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147. Trezza,John, Through chip connection.

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148. Dugas, Roger; Trezza, John, Tooling for coupling multiple electronic chips.

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149. Trezza, John, Triaxial through-chip connection.

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150. Trezza, John, Triaxial through-chip connection.

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151. Glenn A. Rinne, Trilayer/bilayer solder bumps and fabrication methods therefor.

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152. Akram, Salman; Wood, Alan G., Under bump metalization pad and solder bump connections.

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153. Akram,Salman; Wood,Alan G., Under bump metallization pad and solder bump connections.

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154. Nagase, Kenji; Kawabata, Kenichi, Wiring structure of printed wiring board and method for manufacturing the same.

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