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Method for making semiconductor device having no die supporting surface

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/56
출원번호 US-0055863 (1993-05-04)
발명자 / 주소
  • Djennas Frank (Austin TX) Nomi Victor K. (Round Rock TX) Pastore John R. (Leander TX) Reeves Twila J. (Austin TX) Postlethwait Les (Lexington TX)
출원인 / 주소
  • Motorola, Inc. (Schaumburg IL 02)
인용정보 피인용 횟수 : 383  인용 특허 : 0

초록

A wire bondable plastic encapsulated semiconductor device (58) having no die supporting surface can be manufactured. In one embodiment, a semiconductor die (22) and a plurality of conductors (12) extending toward the periphery of the die are provided. The die is rigidly held in place on a workholder

대표청구항

A method for fabricating a semiconductor device comprising the steps of: placing a semiconductor die having an active surface and a periphery on a supporting workholder; attaching an inactive surface of the semiconductor die to a removable tape, the tape being supported by the workholder to rigidly

이 특허를 인용한 특허 (383)

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  218. Paek, Jong Sik; Do, Won Chul; Park, Doo Hyun; Park, Eun Ho; Oh, Sung Jae, Semiconductor device and manufacturing method thereof.
  219. Ryu, Ji Yeon; Kim, Byong Jin; Shim, Jae Beum, Semiconductor device and manufacturing method thereof.
  220. Do, Won Chul; Ko, Yong Jae, Semiconductor device comprising a conductive pad on a protruding-through electrode.
  221. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connected arrangement between a semiconductor pellet and base substrate electrodes.
  222. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes.
  223. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof.
  224. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof.
  225. Nakamura, Atsushi; Nishi, Kunihiko, Semiconductor device having an improved connection arrangement between a semiconductor pellet and base substrate electrodes and a method of manufacture thereof.
  226. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  227. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  228. Kim, Jin Seong; Park, Dong Joo; Kim, Kwang Ho; Yoo, Hee Yeoul; Jeong, Jeong Wung, Semiconductor device having overlapped via apertures.
  229. Do, Won Chul; Jung, Yeon Seung; Ko, Yong Jae, Semiconductor device having through electrodes protruding from dielectric layer.
  230. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
  231. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  232. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  233. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
  234. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  235. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  236. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  237. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  238. Kim, Gi Jeong; Kim, Jae Yoon; Lee, Kyu Won, Semiconductor device including leadframe with downsets.
  239. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  240. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  241. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  242. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  243. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
  244. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  245. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  246. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory card.
  247. DiCaprio, Vincent; Kaskoun, Kenneth, Semiconductor memory cards and method of making same.
  248. Seo, Seong Min; Chung, Young Suk; Paek, Jong Sik; Ku, Jae Hun; Yee, Jae Hak, Semiconductor package.
  249. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  250. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  251. Kelly, Michael; Hiner, David; Huemoeller, Ronald; St. Amand, Roger, Semiconductor package and fabricating method thereof.
  252. Kim,Do Hyung; Jeon,Hyung Il; Park,Doo Hyun, Semiconductor package and its manufacturing method.
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  254. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent, Semiconductor package and method for fabricating the same.
  255. Shin, Won Sun; Lee, Seon Goo; Chun, Do Sung; Jang, Tae Hoan; DiCaprio, Vincent D., Semiconductor package and method for fabricating the same.
  256. Shin,Won Sun; Chun,Do Sung; Lee,Sang Ho; Lee,Seon Goo; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  257. Shin,Won Sun; Chun,Do Sung; Lee,Soon Goo; Shim,Il Kwon; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  258. Shin,Won Sun; Lee,Seon Goo; Chun,Do Sung; Jang,Tae Hoan; DiCaprio,Vincent, Semiconductor package and method for fabricating the same.
  259. WonSun Shin KR; DoSung Chun TH; SangHo Lee KR; SeonGoo Lee KR; Vincent DiCaprio, Semiconductor package and method for fabricating the same.
  260. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  261. Paek, Jong Sik, Semiconductor package and method for manufacturing the same.
  262. Shin, WonSun; Chun, DoSung; Lee, SeonGoo; Lee, SangHo; DiCaprio, Vincent, Semiconductor package and method for manufacturing the same.
  263. WonSun Shin KR; DoSung Chun TH; SeonGoo Lee KR; SangHo Lee KR; Vincent DiCaprio, Semiconductor package and method for manufacturing the same.
  264. Jae Hak Yee KR; Young Suk Chung KR; Jae Jin Lee KR; Terry Davis ; Chung Suk Han KR; Jae Hun Ku KR; Jae Sung Kwak KR; Sang Hyun Ryu KR, Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant.
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  267. Kim,Young Ho; Choi,Seok Hyun; Lee,Choon Heung; Park,Sung Su; Park,Sung Soon, Semiconductor package and method of manufacturing the same which reduces warpage.
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  269. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
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  271. Huemoeller,Ronald Patrick; Hiner,David Jon; Rusli,Sukianto, Semiconductor package and substrate having multi-level vias fabrication method.
  272. John W. Smith ; Christopher M. Pickett, Semiconductor package assemblies with moisture vents and methods of making same.
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  274. Lee, Sun Goo; Lee, Choon Heung; Lee, Sang Ho, Semiconductor package exhibiting efficient lead placement.
  275. Cha Gi Bon,KRX, Semiconductor package for a semiconductor chip having centrally located bottom bond pads.
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  279. Smith, Lee J., Semiconductor package having leadframe with exposed anchor pads.
  280. Fjelstad, Joseph, Semiconductor package having light sensitive chips.
  281. Fjelstad,Joseph, Semiconductor package having light sensitive chips.
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  283. Lee,Tae Heon; Seo,Mu Hwan, Semiconductor package having reduced thickness.
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  285. Heo, Young Wook, Semiconductor package having stacked semiconductor chips and method of making the same.
  286. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
  287. Scanlan, Christopher M.; Berry, Christopher J., Semiconductor package in package.
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  289. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  290. Scanlan, Christopher Marc; Huemoeller, Ronald Patrick, Semiconductor package including a top-surface metal layer for implementing circuit features.
  291. Paek, Jong Sik, Semiconductor package including flip chip.
  292. Paek,Jong Sik, Semiconductor package including flip chip.
  293. Foster, Donald Craig, Semiconductor package including isolated ring structure.
  294. Lee,Seung Ju; Do,Won Chul; Lee,Kwang Eung, Semiconductor package including leads and conductive posts for providing increased functionality.
  295. Yang, Jun Young; Lee, Sun Goo; Lee, Choon Heung, Semiconductor package including low temperature co-fired ceramic substrate.
  296. Lee,Sang Ho; Yang,Jun Young; Lee,Seon Goo; Hyun,Jong Hae; Lee,Choon Heung, Semiconductor package including passive elements and method of manufacture.
  297. Miks, Jeffrey Alan, Semiconductor package including ring structure connected to leads with vertically downset inner ends.
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  299. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
  300. Hiner, David Jon; Huemoeller, Ronald Patrick; Rusli, Sukianto, Semiconductor package including top-surface terminals for mounting another semiconductor package.
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  302. Park, Sung Soon; Jang, Sang Jae; Lee, Choon Heung; Lee, Seon Goo; Sohn, Eun Sook; Park, Sung Su, Semiconductor package structure reducing warpage and manufacturing method thereof.
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  309. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
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  311. Lee,Choon Heung; Foster,Donald C.; Choi,Jeoung Kyu; Kim,Wan Jong; Youn,Kyong Hoon; Lee,Sang Ho; Lee,Sun Goo, Semiconductor package with increased number of input and output pins.
  312. Jeong, Jung Ho; Hong, Jong Chul; Kim, Eun Deok, Semiconductor package with optimized leadframe bonding strength.
  313. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  314. Hu, Tom; Davis, Terry W.; Bancod, Ludovico, Semiconductor package with singulation crease.
  315. Markus K. Liebhard, Semiconductor package with warpage resistant substrate.
  316. Fjelstad, Joseph, Semiconductor packages having light-sensitive chips.
  317. Kiritani, Mika, Semiconductor resin molding method.
  318. Yoo, Duc Su, Shield cap and semiconductor package including shield cap.
  319. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  320. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
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  322. Darveaux, Robert Francis; St. Amand, Roger D.; Perelman, Vladimir, Stackable package and method.
  323. Bancod, Ludovico E.; Kim, Jin Seong; Wachtler, Kurt Peter, Stackable plasma cleaned via package and method.
  324. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable protruding via package and method.
  325. Crowley,Sean Timothy; Alvarez,Angel Orabuena; Yang,Jun Young, Stackable semiconductor package and method for manufacturing same.
  326. Heo, Byong II, Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same.
  327. Shin,WonSun; Chun,DoSung; Lee,SangHo; Lee,SeonGoo; DiCaprio,Vincent, Stackable semiconductor package having semiconductor chip within central through hole of substrate.
  328. Scanlan, Christopher M.; Berry, Christopher J., Stackable semiconductor package including laminate interposer.
  329. Darveaux, Robert Francis; Bancod, Ludovico; Yoshida, Akito, Stackable treated via package and method.
  330. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  331. Yoshida, Akito; Dreiza, Mahmoud, Stackable variable height via package and method.
  332. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  333. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  334. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  335. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  336. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  337. Yoshida, Akito; Dreiza, Mahmoud; Zwenger, Curtis Michael, Stackable via package and method.
  338. Kuo, Bob Shih-Wei; Dunlap, Brett Arnold; Troche, Jr., Louis B.; Syed, Ahmer; Shumway, Russell, Stacked and staggered die MEMS package and method.
  339. Huemoeller,Ronald Patrick; Rusli,Sukianto; Hiner,David Jon, Stacked embedded leadframe.
  340. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  341. Longo, Joseph Marco; Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  342. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
  343. Scanlan, Christopher M., Stacked redistribution layer (RDL) die assembly package.
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  350. Farnworth, Warren M., Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece.
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  358. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  359. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  360. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  361. Hiner, David Jon; Huemoeller, Ronald Patrick, Through via connected backside embedded circuit features structure and method.
  362. Huemoeller, Ronald Patrick; Reed, Frederick Evans; Hiner, David Jon; Lee, Kiwook, Through via nub reveal method and structure.
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  364. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  365. Hiner, David Jon; Huemoeller, Ronald Patrick; Kelly, Michael G., Through via recessed reveal structure and method.
  366. Huemoeller, Ronald Patrick; Lie, Russ; Hiner, David, Two-sided fan-out wafer escape package.
  367. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
  368. Huemoeller,Ronald Patrick; Lie,Russ; Hiner,David, Two-sided wafer escape package.
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  371. Sally Y. L. Foong ; Kok Khoon Ho MY, Using removable spacers to ensure adequate bondline thickness.
  372. Dunaway Thomas J. ; Cullinan Deborah A., Vacuum die bond for known good die assembly.
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  374. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  375. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  376. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  377. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  378. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  379. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  380. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  381. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package and fabrication method.
  382. Huemoeller,Ronald Patrick; Rusli,Sukianto; Razu,David, Wafer level package and fabrication method.
  383. Huemoeller, Ronald Patrick; Rusli, Sukianto; Razu, David, Wafer level package fabrication method.
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