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Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/41
  • H01L-023/544
  • H01L-021/66
출원번호 US-0407052 (1995-03-17)
우선권정보 JP-0221822 (1991-09-02)
발명자 / 주소
  • Yoshizaki Thutomu (Kawasaki JPX)
출원인 / 주소
  • Fujitsu Limited (Kawasaki JPX 03)
인용정보 피인용 횟수 : 146  인용 특허 : 0

초록 ▼

A semiconductor chip for mounting on a package substrate by a flip-chip process includes a plurality of electrode pads of a first group provided on a major surface of the semiconductor chip for external electrical connection such that the electrode pads of the first group cover a major surface of th

대표청구항 ▼

A semiconductor chip for mounting on a package substrate by a flip-chip process, comprising: a plurality of electrode pads of a first group provided on a major surface of said semiconductor chip for external electrical connection, each of said electrode pads of said first group having a first size a

이 특허를 인용한 특허 (146)

  1. Payne, Alexander; Miller, Gregory, 2-D diffraction grating for substantially eliminating polarization dependent losses.
    상세보기
  2. Amm, David T., Angled illumination for a single order light modulator based projection system.
    상세보기
  3. Trisnadi, Jahja I.; Carlisle, Clinton B., Apparatus for selectively blocking WDM channels.
    상세보기
  4. Maheshwari,Dinesh, Arbitrary phase profile for better equalization in dynamic gain equalizer.
    상세보기
  5. Amm, David T.; Trisnadi, Jahja; Hunter, James; Gudeman, Christopher; Maheshwari, Dinesh, Blazed grating light valve.
    상세보기
  6. Lin, Charles Wen Chyang, Bumpless flip chip assembly with solder via.
    상세보기
  7. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips and via-fill.
    상세보기
  8. Lin Charles Wen Chyang,SGX, Bumpless flip chip assembly with strips and via-fill.
    상세보기
  9. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.
    상세보기
  10. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.
    상세보기
  11. Lee, Jin-Yuan; Lin, Mou-Shiung; Huang, Ching-Cheng, Chip structure and process for forming the same.
    상세보기
  12. Maheshwari, Dinesh; Trisnadi, Jahia; Corrigan, Robert W., Chirped optical MEM device.
    상세보기
  13. Leung, Omar; Amm, David T., Controlled curvature of stressed micro-structures.
    상세보기
  14. Ichikawa Kinya,JPX ; Seki Seiichiroh,JPX ; Miwa Takaya,JPX ; Mashimoto Yohko,JPX, Design for flip chip joint pad/LGA pad.
    상세보기
  15. Dischiano John, Device for removing a flip chip die from packaging.
    상세보기
  16. Maheshwari, Dinesh, Diffractive light modulator with dynamically rotatable diffraction plane.
    상세보기
  17. Trisnadi,Jahja I.; Carlisle,Clinton B.; Cejna,Vlastimil, Diffractive light modulator-based dynamic equalizer with integrated spectral monitor.
    상세보기
  18. Dave B. Corbin ; Eric Bogatin, Electrical interface to integrated circuit device having high density I/O count.
    상세보기
  19. Hsu Chen-Chung,TWX, Electromigration test pattern simulating semiconductor components.
    상세보기
  20. Miller, Gregory; Berger, Josef, Fiber optic transceiver.
    상세보기
  21. Hino Atsushi,JPX ; Naito Toshiki,JPX ; Sugimoto Masakazu,JPX, Film carrier and semiconductor device using same.
    상세보기
  22. Ouchi Kazuo,JPX ; Morita Shoji,JPX ; Hino Atsushi,JPX ; Sugimoto Masakazu,JPX, Film carrier, semiconductor device using same and method for mounting semiconductor element.
    상세보기
  23. Charles W. C. Lin SG, Flip chip assembly with via interconnection.
    상세보기
  24. Charles W. C. Lin SG, Flip chip assembly with via interconnection.
    상세보기
  25. Tomita,Akira; Amm,David Thomas; Daneman,Michael J.; Hunter,James; Staker,Bryan, High contrast grating light valve type device.
    상세보기
  26. Maheshwari,Dinesh, High contrast tilting ribbon blazed grating.
    상세보기
  27. Jamieson, Mark P., High-density flip-chip interconnect.
    상세보기
  28. Humphrey Guy H. ; Fisher Rory L. ; D'Amato Jerry, Integrated circuit having unique lead configuration.
    상세보기
  29. Hunter, James A., Integrated driver process flow.
    상세보기
  30. Carlisle, Clinton B.; Trisnadi, Jahia I.; Hunter, James, Light modulator structure for producing high-contrast operation using zero-order light.
    상세보기
  31. Trisnadi,Jahja I.; Carlisle,Clinton B., MEMS interferometer-based reconfigurable optical add-and-drop multiplexor.
    상세보기
  32. Lu, Chun-Lin; Wu, Kai-Chiang; Liu, Ming-Kai; Wang, Yen-Ping; Liang, Shih-Wei; Yang, Ching-Feng; Miao, Chia-Chun; Lin, Hung-Jen, Mechanisms for forming hybrid bonding structures with elongated bumps.
    상세보기
  33. Lu, Chun-Lin; Wu, Kai-Chiang; Liu, Ming-Kai; Wang, Yen-Ping; Liang, Shih-Wei; Yang, Ching-Feng; Miao, Chia-Chun; Lin, Hung-Jen, Mechanisms for forming hybrid bonding structures with elongated bumps.
    상세보기
  34. Berlin Claude L. ; Howell Wayne J., Metallization structure for altering connections.
    상세보기
  35. Trisnadi, Jahja I.; Carlisle, Clinton B., Method and apparatus for dynamic equalization in wavelength division multiplexing.
    상세보기
  36. de Groot, Wilhelmus; Maheshwari, Dinesh, Method and apparatus for leveling thermal stress variations in multi-layer MEMS devices.
    상세보기
  37. Trisnadi, Jahja I., Method and apparatus for reducing laser speckle using polarization averaging.
    상세보기
  38. Amm, David T., Method and device for modulating a light beam and having an improved gamma response.
    상세보기
  39. Miller, Gregory D., Method for domain patterning in low coercive field ferroelectrics.
    상세보기
  40. Lin, Charles W. C., Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly.
    상세보기
  41. Yamaha, Takahisa, Method for manufacturing a semiconductor device.
    상세보기
  42. Wilhard Von Wendorff DE; Albrecht Mayer DE, Method for producing emulation circuit configuration, and configuration with two integrated circuits.
    상세보기
  43. Val Christian,FRX ; Campenhout Yves Van,FRX ; Gilet Dominique,FRX, Method for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device.
    상세보기
  44. Shook, James Gill, Method of and apparatus for sealing an hermetic lid to a semiconductor die.
    상세보기
  45. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip.
    상세보기
  46. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace to a semiconductor chip.
    상세보기
  47. Charles W. C. Lin SG; Cheng-Lien Chiang TW, Method of connecting a bumped conductive trace to a semiconductor chip.
    상세보기
  48. Lin, Charles W. C., Method of connecting a conductive trace and an insulative base to a semiconductor chip.
    상세보기
  49. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
    상세보기
  50. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.
    상세보기
  51. Charles W. C. Lin SG, Method of connecting a conductive trace to a semiconductor chip.
    상세보기
  52. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip.
    상세보기
  53. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using a metal base.
    상세보기
  54. Lin,Charles W. C., Method of connecting a conductive trace to a semiconductor chip using conductive adhesive.
    상세보기
  55. Chiang, Cheng-Lien; Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching.
    상세보기
  56. Lin,Charles W. C.; Chiang,Cheng Lien, Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip.
    상세보기
  57. Yamaha,Takahisa, Method of forming a bonding pad structure.
    상세보기
  58. Yamaha,Takahisa, Method of forming a bonding pad structure.
    상세보기
  59. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly.
    상세보기
  60. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly.
    상세보기
  61. Lin, Charles W. C., Method of making a pillar in a laminated structure for a semiconductor chip assembly.
    상세보기
  62. Charles W. C. Lin SG, Method of making a semiconductor chip assembly.
    상세보기
  63. Lin, Charles W. C., Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive.
    상세보기
  64. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a bumped metal pillar.
    상세보기
  65. Lin,Charles W. C.; Chen,Cheng Chung, Method of making a semiconductor chip assembly with a bumped terminal and a filler.
    상세보기
  66. Lin, Charles W. C.; Chen, Cheng-Chung, Method of making a semiconductor chip assembly with a bumped terminal, a filler and an insulative base.
    상세보기
  67. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a carved bumped terminal.
    상세보기
  68. Wang, Chia-Chung; Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace and a substrate.
    상세보기
  69. Charles W. C. Lin SG, Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
    상세보기
  70. Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.
    상세보기
  71. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a laterally aligned bumped terminal and filler.
    상세보기
  72. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.
    상세보기
  73. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.
    상세보기
  74. Chiang,Cheng Lien; Lin,Charles W. C., Method of making a semiconductor chip assembly with an embedded metal particle.
    상세보기
  75. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.
    상세보기
  76. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.
    상세보기
  77. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.
    상세보기
  78. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.
    상세보기
  79. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
    상세보기
  80. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.
    상세보기
  81. Charles W. C. Lin SG, Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly.
    상세보기
  82. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.
    상세보기
  83. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.
    상세보기
  84. Corbin Dave B. ; Bogatin Eric, Method of producing an electrical interface to an integrated circuit device having high density I/O count.
    상세보기
  85. Leung, Omar S., Method of sealing a hermetic lid to a semiconductor die at an angle.
    상세보기
  86. Trisnadi, Jahja I., Method, apparatus, and diffuser for reducing laser speckle.
    상세보기
  87. Hunter,Jim; Amm,David; Gudeman,Christopher, Micro-structures with individually addressable ribbon pairs.
    상세보기
  88. Gudeman, Christopher; Hunter, James; Yeh, Richard; Amm, David T., Micro-support structures.
    상세보기
  89. Bruner,Mike, Microelectronic mechanical system and methods.
    상세보기
  90. Bruner,Mike; Yeh,Richard; Hunter,Jim, Microelectronic mechanical system and methods.
    상세보기
  91. Shafaat, Syed Tariq; Carlisle, Clinton B.; Hartranft, Marc, Optical communication arrangement.
    상세보기
  92. Alioshin, Paul; Corbin, Dave B.; Tomita, Akira; Corrigan, Robert W., Optical device arrays with optimized image resolution.
    상세보기
  93. Maheshwari, Dinesh; Dueweke, Michael, PDL mitigation structure for diffractive MEMS and gratings.
    상세보기
  94. Dueweke, Michael; Maheshwari, Dinesh; Gudernan, Christopher; Trisnadi, Jahja I., Patterned diffractive light modulator ribbon for PDL reduction.
    상세보기
  95. Gudeman,Christopher; Leung,Omar; Hunter,James; Amm,David, Pre-deflected bias ribbons.
    상세보기
  96. Carlisle, Clinton B.; Trisnadi, Jahja I., Rapidly tunable external cavity laser.
    상세보기
  97. Trisnadi,Jahja I.; Carlisle,Clinton B., Reconfigurable modulator-based optical add-and-drop multiplexer.
    상세보기
  98. Hunter, James; Staker, Bryan, Reduced formation of asperities in contact micro-structures.
    상세보기
  99. Tomita Yasuhiro,JPX, Semiconductor chip and semiconductor wafer having power supply pads for probe test.
    상세보기
  100. Charles W. C. Lin SG, Semiconductor chip assembly with ball bond connection joint.
    상세보기
  101. Lin, Charles W. C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.
    상세보기
  102. Lin, Charles W.C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.
    상세보기
  103. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with bumped metal pillar.
    상세보기
  104. Charles W. C. Lin SG, Semiconductor chip assembly with bumped molded substrate.
    상세보기
  105. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with bumped terminal and filler.
    상세보기
  106. Lin, Charles W. C.; Chen, Cheng Chung, Semiconductor chip assembly with bumped terminal, filler and insulative base.
    상세보기
  107. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with carved bumped terminal.
    상세보기
  108. Wang, Chia-Chung; Lin, Charles W. C., Semiconductor chip assembly with chip in substrate cavity.
    상세보기
  109. Lin, Charles W. C., Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit.
    상세보기
  110. Chiang,Cheng Lien; Lin,Charles W. C., Semiconductor chip assembly with embedded metal particle.
    상세보기
  111. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.
    상세보기
  112. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.
    상세보기
  113. Lin, Charles W. C., Semiconductor chip assembly with hardened connection joint.
    상세보기
  114. Lin, Charles W. C., Semiconductor chip assembly with interlocked conductive trace.
    상세보기
  115. Lin, Charles W.C., Semiconductor chip assembly with interlocked conductive trace.
    상세보기
  116. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with interlocked contact terminal.
    상세보기
  117. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Semiconductor chip assembly with laterally aligned bumped terminal and filler.
    상세보기
  118. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with laterally aligned filler and insulative base.
    상세보기
  119. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with metal containment wall and solder terminal.
    상세보기
  120. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with precision-formed metal pillar.
    상세보기
  121. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.
    상세보기
  122. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.
    상세보기
  123. Charles W. C. Lin SG, Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.
    상세보기
  124. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.
    상세보기
  125. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar.
    상세보기
  126. Lin, Charles W. C.; Chen, Cheng-Chung, Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal.
    상세보기
  127. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with welded metal pillar of stacked metal balls.
    상세보기
  128. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond.
    상세보기
  129. Kazutami Arimoto JP, Semiconductor chip scale package and ball grid array structures.
    상세보기
  130. Matsuda, Shuichi, Semiconductor device.
    상세보기
  131. Fujiki Noriaki,JPX ; Yamashita Takashi,JPX, Semiconductor device and bonding pad structure therefor.
    상세보기
  132. Tsuji Kazuto,JPX ; Yoneda Yoshiyuki,JPX ; Sakoda Hideharu,JPX ; Nomoto Ryuuji,JPX ; Watanabe Eiji,JPX ; Orimo Seiichi,JPX ; Onodera Masanori,JPX ; Kasai Junichi,JPX, Semiconductor device including a frame terminal.
    상세보기
  133. Akito Yoshida JP, Semiconductor device with flip-chip structure and method of manufacturing the same.
    상세보기
  134. Ulrich Bruce Dale ; Nguyen Tue ; Kobayashi Masato, Semiconductor wafer with removed CVD copper.
    상세보기
  135. Hunter,James; Gudeman,Christopher S., Silicon substrate as a light modulator sacrificial layer.
    상세보기
  136. Lin, Charles W. C., Support circuit with a tapered through-hole for a semiconductor chip assembly.
    상세보기
  137. Lee Daniel Hao-Tien,TWX, Testchip design for process analysis in sub-micron DRAM fabrication.
    상세보기
  138. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.
    상세보기
  139. Maheshwari, Dinesh, Tilt-able grating plane for improved crosstalk in 1×N blaze switches.
    상세보기
  140. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  141. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  142. Lin, Mou-Shiung, Top layers of metal for high performance IC's.
    상세보기
  143. Lin, Mou-Shiung; Lee, Jin-Yuan, Top layers of metal for high performance IC's.
    상세보기
  144. Corrigan,Robert W.; Maheshwari,Dinesh, Two-stage gain equalizer.
    상세보기
  145. Crumly William R., Wafer scale burn-in socket.
    상세보기
  146. Roxlo, Charles B., Wavelength selective switch and equalizer.
    상세보기

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