[특허]Arrangement having multilevel wiring structure used for electronic component module

Arrangement having multilevel wiring structure used for electronic component module 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H01L-039/02
출원번호	US-0098074 (1993-07-28)
우선권정보	JP-0203856 (1992-07-30); JP-0083573 (1993-04-09)
발명자 / 주소	Sudo Toshio (Kawasaki JPX) Ito Kenji (Kawasaki JPX)
출원인 / 주소	Kabushiki Kaisha Toshiba (Kawasaki JPX 03)
인용정보	피인용 횟수 : 43 인용 특허 : 0

초록 ▼

According to this invention, there is provided a multilevel wiring substrate comprising, a base substrate having first and second surface and including first and second areas, said first area including first and second level conductive layers insulated from each other, a plurality of first vertical conductive layers electrically connected to said first level conductive layer so as to provide first end portions exposed to said first surface, and a plurality of second vertical conductive layers electrically connected to said second level conductive layer so as to provide second end portions exposed to said first surface, said first and second end portions being alternately arranged in row and column directions, and said second area including third and fourth conductive layers.

대표청구항 ▼

An arrangement having a multilevel wiring structure used for an electronic component module comprising: a base substrate having first and second surfaces opposed each other, said substrate including first multilevel conductive patterns and first vertical conductive paths for electrical connections exposed to said first and second surfaces, said first vertical conductive paths being located at a peripheral section of said base substrate so as to surround said first multilevel conductive patterns; and a thin film wiring layer having a third surface for mounting a plurality of electronic components having arbitrary sizes at arbitrary positions respectively, and a fourth surface formed on said first surface of said base substrate, said thin film wiring layer including second multilevel conductive patterns having portions for electrical connections exposed to said third and fourth surfaces; wherein said portions for electrical connections are selected such that electrical signals and power supply voltages supplied from said base substrate are applied to said electronic components through said thin film wiring layer; and wherein said first multilevel conductive patterns include first and second potential level conductive layers insulated from each other, a plurality of second vertical conductive paths electrically connected to said first potential level conductive layers so as to provide first end portions exposed to said first surface of said base substrate, and a plurality of third vertical conductive paths electrically connected to said second potential level conductive layers so as to provide second end portions exposed to said first surface of said base substrate, said first and second end portions being alternately arranged in row and column directions so as to provide closest connections with said electrical components through said thin film wiring layer.

이 특허를 인용한 특허 (43)

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Liberkowski Janusz B. (5884 Macadam Ct. San Jose CA 95123), Lattice interconnect method and apparatus for manufacturing multi-chip modules.
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Herrell, Dennis J.; Dolbear, Thomas P., Low inductance power distribution system for an integrated circuit chip.
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deRochemont, L. Pierre; Farmer, Peter H., Method of manufacture of ceramic composite wiring structures for semiconductor devices.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
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저장형식	Text(ASCII format) Excel format PIAS분석(.xls)
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

Arrangement having multilevel wiring structure used for electronic component module 원문보기

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연구과제 타임라인

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Arrangement having multilevel wiring structure used for electronic component module 원문보기

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이 특허를 인용한 특허 (43)

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