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| 국가/구분 | United States(US) Patent 등록 |
|---|---|
| 국제특허분류(IPC7판) |
|
| 출원번호 | US-0324295 (1994-10-17) |
| 발명자 / 주소 |
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| 출원인 / 주소 |
|
| 인용정보 | 피인용 횟수 : 331 인용 특허 : 0 |
A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which co
A Parallel RISC computer system is provided by a multi-mode dynamic multi-mode parallel processor array with one embodiment illustrating a tightly coupled VLSI embodiment with an architecture which can be extended to more widely placed processing elements through the interconnection network which couples multiple processors capable of MIMD mode processing to one another with broadcast of instructions to selected groups of units controlled by a controlling processor. The coupling of the processing elements logic enables dynamic mode assignment and dynamic mode switching, allowing processors operating in a SIMD mode to make maximum memory and cycle time usage. On and instruction by instruction level basis, modes can be switched from SIMD to MIMD, and even into SISD mode on the controlling processor for inherently sequential computation allowing a programmer or complier to build a program for the computer system which uses the optimal kind of parallelism (SISD, SIMD, MIMD). Furthermore, this execution, particularly in the SIMD mode, can be set up for running applications at the limit of memory cycle time. With the ALLNODE switch and alternatives paths a system can be dynamically achieved in a few cycles for many many processors. Each processing element and memory and has MIMD capability the processor\s an instruction register, condition register and program counter provide common resources which are used in MIMD and SIMD. The program counter become a base register in SIMD mode.
A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter
A dynamic multi-mode parallel processing array, comprising: a plurality of processors, each processor having a control unit for decoding and executing instructions of an instruction set, a data flow unit and a local memory, each of said control units having an instruction register, a program counter, a condition code register and a parallel mode bit (PMB), the PMB indicating whether the processor obtains instructions from a controlling processor or from said local memory; an interconnection path between the instruction registers of the processors; the instruction set having a plurality of instructions, each instruction having a parallel execution type bit (PET) that is used in conjunction with the PMB by the control unit to determine whether an instruction should be executed, the instruction set having a switch mode instruction for changing the PMB bit of a processor executing the instruction; the processors organized into one or more groups, each group having a processor configured as the controlling processor, wherein any processor in the plurality of processors can be dynamically configured as the controlling processor, the controlling processor enabling the processors of a group to operate in a MIMD or SIMD mode, and to switch modes dynamically on an instruction-by, instruction basis; and when a group of processors are operating in SIMD mode the controlling processor provides instructions to the instruction registers of the other processors in the group, each instruction provided via the interconnection path when the controlling processor fetches the instruction; and wherein the PMB indicates SIMD and MIMD modes and the PET indicates local and array operations of the associated processor.
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