이 특허를 인용한 특허 (275)

1. Kardos Gabor, Adapter which emulates ball grid array packages.

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2. Anthony,William M., Amalgam of shielding and shielded energy pathways and other elements for single or multiple circuitries with common reference node.

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3. Anthony,William M., Amalgam of shielding and shielded energy pathways and other elements for single or multiple circuitries with common reference node.

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4. Ashman, John J.; Waymer, Monroe; Hammond, Jennifer, Apparatus and method for making electrical connectors.

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5. Ashman, John J.; Waymer, Monroe; Hammond, Jennifer, Apparatus and methods for retaining and placing electrical components.

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6. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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7. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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8. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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9. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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10. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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11. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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12. Anthony, Anthony A.; Anthony, William M., Arrangement for energy conditioning.

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13. Anthony, Jr.,Anthony A.; Anthony,William M., Arrangement for energy conditioning.

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14. Anthony,Anthony A.; Anthony,William M., Arrangement for energy conditioning.

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15. Anthony,Anthony A.; Anthony,William M., Arrangement for energy conditioning.

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16. Anthony, Anthony A.; Anthony, William M., Arrangements for energy conditioning.

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17. Klein Dean A., Assembly aid for mounting packaged integrated circuit devices to printed circuit boards.

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18. Klein Dean A., Assembly aid for mounting packaged integrated circuit devices to printed circuit boards.

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19. Keller, Rex W., Ball grid array connection device.

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20. Murphy James V., Ball grid array including modified hard ball contacts and apparatus for attaching hard ball contacts to a ball grid arra.

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21. Lin Patrick,TWX, Ball-grid array IC packaging frame.

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22. Lin, Charles Wen Chyang, Bumpless flip chip assembly with solder via.

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23. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips and via-fill.

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24. Lin Charles Wen Chyang,SGX, Bumpless flip chip assembly with strips and via-fill.

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25. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.

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26. Charles Wen Chyang Lin SG, Bumpless flip chip assembly with strips-in-via and plating.

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27. Mahajan Ravi V. ; Xie Hong ; Delaplane Neil C. ; James Gregory A., Cartridge and an enclosure for a semiconductor package.

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28. Lee Michael Guang-Tzong ; Beilin Solomon I. ; Wang Wen-chou Vincent, Chip and board stress relief interposer.

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29. Yasuhito Anzai JP, Circuit assembly including VLSI package.

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30. Memis Irving, Circuit board with primary and secondary through holes.

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31. Alcoe, David J., Compliant laminate connector.

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32. Anthony, Anthony A., Component carrier.

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33. Anthony,Anthony A., Component carrier.

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34. Anthony,Anthony A.; Anthony,William M., Component carrier.

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35. Anthony,Anthony; Anthony,William M., Component carrier.

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36. Anthony,Anthony; Anthony,William M., Component carrier.

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37. Rathburn, James J., Composite contact for fine pitch electrical interconnect assembly.

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38. Rathburn, James J., Composite contact for fine pitch electrical interconnect assembly.

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39. Peters, Michael G.; McCormack, Mark Thomas; Bernales, Aris, Composite interposer and method for producing a composite interposer.

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40. Anthony, William M., Conditioner with coplanar conductors.

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41. Anthony, William M., Conditioner with coplanar conductors.

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42. Costello, Brian Patrick, Connector assembly having a connector extender module.

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43. Wilson, Peter Paul; Chau, Phuc Steve; Herring, Michael David; Knaub, John Edward, Connector assembly having a mating adapter.

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44. Harper, Jr., Donald K.; Johnson, Lewis Robin, Connector housing for electrical connector.

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45. Harper, Jr., Donald K.; Johnson, Lewis Robin, Connector housing for electrical connector.

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46. Anthony,Anthony, Connector related structures including an energy conditioner.

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47. Scandiuzzo, Mauro; Perilli, Luca; Canegallo, Roberto, Contact and contactless differential I/O pads for chip-to-chip communication and wireless probing.

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48. Lemke Timothy A. ; Houtz Timothy W. ; Gross Charles M. ; Neidert Kenneth A., Contact for use in an electrical connector.

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49. Paulsen, Erik; Page, William; Otto, Erich S., Converter device.

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50. Shibayama,Katsumi, Detector.

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51. Bedos Jean-Philippe,FRX ; Sune Gerard,FRX, Device and method for interconnection between two electronic devices.

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52. Sturcken, Keith K.; Hughes, John A.; Love, Thomas E.; Konecke, Sheila J.; Montag, Jeffrey; Wallace, Peter M., Devices and methods for stacking individually tested devices to form multi-chip electronic modules.

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53. Hermeline, Nicolas; Flers, Alain; Barlerin, Stephane; Stricot, Yves, Dismountable optical coupling device.

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54. Zerebilov, Arkady Y.; Ingram, Deborah A.; Lord, Hung-Wei; Buck, Jonathan E.; Stoner, Stuart C.; Ellison, Jason J., Electrical cable connector.

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55. Zerebilov, Arkady Y.; Ingram, Deborah A.; Lord, Hung-Wei; Buck, Jonathan E.; Stoner, Stuart C.; Ellison, Jason J., Electrical cable connector.

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56. Zerebilov, Arkady Y.; Ingram, Deborah A.; Lord, Hung-Wei; Buck, Jonathan E.; Stoner, Stuart C.; Ellison, Jason J., Electrical cable connector.

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57. Zerebilov, Arkady Y.; Lord, Hung-Wei; Buck, Jonathan E.; Stoner, Stuart C., Electrical cable connector.

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58. Harper, Jr., Donald K.; Johnson, Lewis Robin, Electrical connector.

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59. Harper, Jr., Donald K.; Johnson, Lewis Robin, Electrical connector.

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60. Horchler, David C., Electrical connector.

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61. Johnescu, Douglas M.; Buck, Jonathan E., Electrical connector having ribbed ground plate.

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62. Johnescu, Douglas M.; Buck, Jonathan E., Electrical connector having ribbed ground plate.

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63. Johnescu, Douglas M.; Buck, Jonathan E., Electrical connector having ribbed ground plate.

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64. Stoner, Stuart C.; Johnescu, Douglas M.; Buck, Jonathan E., Electrical connector having ribbed ground plate with engagement members.

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65. Horchler, David C., Electrical connector housing.

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66. Horchler, David C.; Johnson, Lewis Robin, Electrical connector with reduced stack height.

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67. Horchler, David C.; Johnson, Lewis Robin, Electrical connector with reduced stack height.

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68. Ashman, John J.; Waymer, Monroe; Hammond, Jennifer, Electrical connectors and electrical components.

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69. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B., Electrical ground shield.

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70. Anthony,Anthony A.; Anthony,William M., Electrode arrangement for circuit energy conditioning.

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71. Cadet Yves,FRX ; Tutka Andre,FRX, Electronic card assembly by means of solder connections.

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72. Koetsu Tamura JP, Electronic circuit package assembly with solder interconnection sheet.

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73. Buck, Jr., Roy Vesper; Bergeron, Joseph Samuel, Electronic package structures and methods.

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74. Anthony, David J., Energy conditioner structures.

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75. Anthony, William M., Energy conditioner with tied through electrodes.

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76. Anthony, William M., Energy conditioner with tied through electrodes.

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77. Anthony, Anthony A.; Anthony, William M., Energy conditioning circuit arrangement for integrated circuit.

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78. Anthony, Anthony A.; Anthony, William M., Energy conditioning circuit arrangement for integrated circuit.

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79. Anthony, Anthony A.; Anthony, William M., Energy conditioning circuit arrangement for integrated circuit.

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80. Anthony, Anthony A.; Anthony, William M.; Musil, Kenneth W., Energy conditioning circuit assembly.

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81. Anthony, Anthony A.; Musil, Kenneth W.; Anthony, William M.; Muccioli, James P.; Anthony, David J., Energy conditioning circuit assembly.

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82. Anthony,Anthony A.; Anthony,William M., Energy conditioning circuit assembly.

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83. Anthony,Anthony; Anthony,William, Energy conditioning structure.

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84. Anthony,William M., Energy pathway arrangement.

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85. Anthony,William M.; Anthony,Anthony A.; Muccioli,James P., Energy pathway arrangement.

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86. Anthony,William M., Energy pathway arrangements for energy conditioning.

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87. Anthony,William M., Energy pathway arrangements for energy conditioning.

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88. Anthony, Anthony, Filter assembly.

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89. Rathburn, James J., Fine pitch electrical interconnect assembly.

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90. Rathburn,James J.; Cavegn,Martin, Fine pitch electrical interconnect assembly.

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91. Rathburn,James J.; Cavegn,Martin, Fine pitch electrical interconnect assembly.

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92. Rathburn,James J.; Cavegn,Martin, Fine pitch electrical interconnect assembly.

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93. Charles W. C. Lin SG, Flip chip assembly with via interconnection.

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94. Charles W. C. Lin SG, Flip chip assembly with via interconnection.

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95. Yoneda Yoshihiro,JPX, Flip-chip mount board and flip-chip mount structure with improved mounting reliability.

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96. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B., Ground shield for a right angle electrical connector.

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97. Lemke Timothy A. ; Houtz Timothy W., High density connector.

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98. Lemke Timothy A. ; Houtz Timothy W., High density connector.

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99. Lemke Timothy A. ; Houtz Timothy W., High density connector and method of manufacture.

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100. Lemke, Timothy A.; Houtz, Timothy W., High density connector and method of manufacture.

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101. Lemke,Timothy A.; Houtz,Timothy W., High density connector and method of manufacture.

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102. Lemke,Timothy A.; Houtz,Timothy W., High density connector and method of manufacture.

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103. Olson Stanley W., High density connector having a ball type of contact surface.

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104. Olson Stanley W., High density connector having a ball type of contact surface.

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105. Craig Iwami ; Jim K. Hall ; Brian R. Mulholland ; Seth Greiner, High density interconnect module.

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106. Wang Wen-chou Vincent ; Takahashi Yasuhito ; Chou William T. ; Peters Michael G. ; Lee Michael G. ; Beilin Solomon, High density signal interposer with power and ground wrap.

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107. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B.; Zerebilov, Arkady Y.; Ingram, Deborah A.; Lord, Hung-Wei; Fulton, Robert Douglas, High speed electrical connector.

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108. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B.; Zerebilov, Arkady Y.; Ingram, Deborah A.; Lord, Hung-Wei; Fulton, Robert Douglas, High speed electrical connector.

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109. Schwiebert Matthew K. ; Hutchison Brian R. ; Chew Geary L. ; Barnett Ron, High-frequency electronic package with arbitrarily-shaped interconnects and integral shielding.

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110. Horiuchi, Michio; Shimizu, Yukio; Sekigawa, Kazunari; Kobayashi, Tsuyoshi, Inductor and manufacturing method thereof.

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111. Trezza, John, Integrated arrays of modulators and lasers on electronics.

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112. Trezza,John, Integrated arrays of modulators and lasers on electronics.

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113. Joseph P. Miller ; Sompong P. Olarig ; Donald J. Stoddard, Integrated circuit device/circuit board connection apparatus.

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114. Miller, Joseph P.; Olarig, Sompong P.; Stoddard, Donald J., Integrated circuit device/circuit board connection apparatus.

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115. Corisis, David J.; Reynolds, Tracy; Slaughter, Michael; Cram, Daniel; Nevill, Leland R., Integrated circuit package alignment feature.

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116. Corisis, David J.; Reynolds, Tracy; Slaughter, Michael; Cram, Daniel; Nevill, Leland R.; King, Jerrold L., Integrated circuit package alignment feature.

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117. Koide, Masateru, Interconnect board, printed circuit board unit, and method.

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118. Shenoy Jayarama N. ; Dandia Sanjay, Interconnect layout pattern for integrated circuit packages and the like.

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119. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.

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120. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.

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121. Anthony, William M.; Anthony, David; Anthony, Anthony, Internally overlapped conditioners.

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122. Anthony, David; Anthony, Anthony; Anthony, William M.; Muccioli, James; Neifeld, Richard A., Internally shielded energy conditioner.

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123. Sundstrom,Lance L., Interposer for compliant interfacial coupling.

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124. Alagaratnam, Maniam; Desai, Kishor V.; Patel, Sunil A., Interposer for semiconductor package assembly.

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125. Maniam Alagaratnam ; Kishor V. Desai ; Sunil A. Patel, Interposer for semiconductor package assembly.

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126. Trezza, John, Laser arrays for high power fiber amplifier pumps.

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127. Gore John G. ; Tolar Neal J. ; Brown Roy B. ; Gopani Sunder, Leadless ceramic chip carrier crosstalk suppression method.

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128. Degani Yinon ; Dudderar Thomas Dixon ; Frye Robert Charles, Low cost ball grid array package.

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129. Chakravorty Kishore K., Low cost chip size package and method of fabricating the same.

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130. Kishore K. Chakravorty, Low cost chip size package and method of fabricating the same.

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131. Elco Richard A. ; Fusselman David F., Low cross talk and impedance controlled electrical connector.

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132. Elco, Richard A.; Lemke, Timothy A.; Houtz, Timothy W., Low cross talk and impedance controlled electrical connector with solder masses.

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133. Lemke Timothy A. ; Houtz Timothy W., Low profile connector.

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134. Lemke Timothy A. ; Houtz Timothy W., Low profile connector.

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135. Chao, Clinton, Low-cost and ultra-fine integrated circuit packaging technique.

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136. Anthony, Anthony A.; Anthony, William M., Manufacture including shield structure.

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137. Pendse,Rajendra D., Method and apparatus for flip chip attachment by post collapse re-melt and re-solidification of bumps.

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138. Lin, Charles W. C., Method for forming a ball bond connection joint on a conductive trace and conductive pad in a semiconductor chip assembly.

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139. Anthony, William M.; Anthony, David; Anthony, Anthony, Method for making internally overlapped conditioners.

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140. Woo Jun-Hwan,KRX, Method for making radio-frequency module by ball grid array package.

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141. Klein Dean A., Method for mounting packaged integrated circuit devices to printed circuit boards.

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142. Lemke Timothy A. ; Houtz Timothy W. ; Gross Charles M. ; Gingrich Charles R., Method for placing contact on electrical connector.

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143. Bruno Murari IT; Ubaldo Mastromatteo IT; Benedetto Vigna IT, Method for the electrical and/or mechanical interconnection of components of a microelectronic system.

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144. Komuro, Yoshiaki, Method manufacturing wiring substrate.

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145. Howarth, James J., Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly.

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146. Howarth,James J., Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly.

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147. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip.

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148. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a bumped compliant conductive trace to a semiconductor chip.

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149. Charles W. C. Lin SG; Cheng-Lien Chiang TW, Method of connecting a bumped conductive trace to a semiconductor chip.

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150. Lin, Charles W. C., Method of connecting a conductive trace and an insulative base to a semiconductor chip.

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151. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.

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152. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of connecting a conductive trace and an insulative base to a semiconductor chip using multiple etch steps.

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153. Charles W. C. Lin SG, Method of connecting a conductive trace to a semiconductor chip.

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154. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip.

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155. Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using a metal base.

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156. Lin,Charles W. C., Method of connecting a conductive trace to a semiconductor chip using conductive adhesive.

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157. Chiang, Cheng-Lien; Lin, Charles W. C., Method of connecting a conductive trace to a semiconductor chip using plasma undercut etching.

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158. Lin,Charles W. C.; Chiang,Cheng Lien, Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip.

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159. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a bumped terminal in a laminated structure for a semiconductor chip assembly.

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160. Lin, Charles W. C.; Chiang, Cheng-Lien, Method of making a contact terminal with a plated metal peripheral sidewall portion for a semiconductor chip assembly.

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161. Lin, Charles W. C., Method of making a pillar in a laminated structure for a semiconductor chip assembly.

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162. Charles W. C. Lin SG, Method of making a semiconductor chip assembly.

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163. Lin, Charles W. C., Method of making a semiconductor chip assembly by joining the chip to a support circuit with an adhesive.

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164. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a bumped metal pillar.

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165. Lin,Charles W. C.; Chen,Cheng Chung, Method of making a semiconductor chip assembly with a bumped terminal and a filler.

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166. Lin, Charles W. C.; Chen, Cheng-Chung, Method of making a semiconductor chip assembly with a bumped terminal, a filler and an insulative base.

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167. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a carved bumped terminal.

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168. Wang, Chia-Chung; Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace and a substrate.

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169. Charles W. C. Lin SG, Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.

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170. Lin, Charles W. C., Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment.

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171. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Method of making a semiconductor chip assembly with a laterally aligned bumped terminal and filler.

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172. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with a metal containment wall and a solder terminal.

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173. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with a precision-formed metal pillar.

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174. Chiang,Cheng Lien; Lin,Charles W. C., Method of making a semiconductor chip assembly with an embedded metal particle.

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175. Wang,Chia Chung; Lin,Charles W. C., Method of making a semiconductor chip assembly with an interlocked contact terminal.

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176. Lin, Charles W. C., Method of making a semiconductor chip assembly with chip and encapsulant grinding.

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177. Lin, Charles W. C.; Wang, Chia-Chung; Sigmond, David M., Method of making a semiconductor chip assembly with metal pillar and encapsulant grinding and heat sink attachment.

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178. Lin,Charles W. C.; Wang,Chia Chung, Method of making a semiconductor chip assembly with thermal conductor and encapsulant grinding.

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179. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.

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180. Charles W. C. Lin SG, Method of making a support circuit for a semiconductor chip assembly.

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181. Charles W. C. Lin SG, Method of making a support circuit with a tapered through-hole for a semiconductor chip assembly.

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182. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar and a conductive interconnect in an encapsulant aperture.

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183. Lin,Charles W. C.; Chiang,Cheng Lien, Method of making a three-dimensional stacked semiconductor package with a metal pillar in an encapsulant aperture.

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184. Robert H. Frantz ; Ramon E. Helms, Method of manufacture for embedded processing subsystem module.

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185. Higashida,Takaaki; Kumagai,Koichi; Matsuo,Takahiro, Method of manufacturing a semiconductor element-mounting board.

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186. Howarth,James J., Method of semiconductor device package alignment and method of testing.

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187. Ikeda Hironobu,JPX ; Yamaguti Yukio,JPX, Mounting structure for one or more semiconductor devices.

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188. Osamu Arai JP, Mounting structure of integrated circuit device having high effect of buffering stress and high reliability of connection by solder, and method of mounting the same.

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189. Anthony, Anthony; Anthony, William M., Multi-functional energy conditioner.

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190. Anthony,Anthony A.; Anthony,William M., Multi-functional energy conditioner.

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191. Hamster, Harald; Trezza, John, Multi-wavelength semiconductor laser arrays and applications thereof.

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192. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.

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193. Matsuda, Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.

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194. Matsuda,Shinji, Multileveled printed circuit board unit including substrate interposed between stacked bumps.

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195. Johnson Morgan T. ; Ekstrom David R., Multiple board package employing solder balis and fabrication method and apparatus.

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196. Downes Stuart, Non-collapsing interconnection for semiconductor devices.

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197. Anthony, Jr., Anthony A.; Anthony, William M., Offset pathway arrangements for energy conditioning.

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198. Dudoff, Greg; Trezza, John, Opto-electronic device integration.

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199. Dudoff, Greg; Trezza, John, Opto-electronic device integration.

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200. Dudoff, Greg; Trezza, John, Opto-electronic device integration.

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201. Dudoff, Greg; Trezza, John, Opto-electronic device integration.

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202. Dudoff, Greg; Trezza, John, Opto-electronic device integration.

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203. Anthony,Anthony A.; Anthony,William M.; Muccioli,James P., PREDETERMINED SYMMETRICALLY BALANCED AMALGAM WITH COMPLEMENTARY PAIRED PORTIONS COMPRISING SHIELDING ELECTRODES AND SHIELDED ELECTRODES AND OTHER PREDETERMINED ELEMENT PORTIONS FOR SYMMETRICALLY BALA.

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204. Anthony, Anthony A., Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package.

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205. Anthony,Anthony A., Paired multi-layered dielectric independent passive component architecture resulting in differential and common mode filtering with surge protection in one integrated package.

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206. Anthony, Jr.,Anthony A.; Anthony,William M., Pathway arrangement.

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207. Roessler Robert Joseph ; Pitzele Lennart Daniel, Power magnetic device employing a leadless connection to a printed circuit board and method of manufacture thereof.

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208. Brodsky, William Louis; Chan, Benson; Gaynes, Michael Anthony; Markovich, Voya Rista, Printed wiring board interposer sub-assembly.

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209. Pai Deepak Keshav ; Rosenstein Leo Marvin ; Lund Lowell Dennis, Process of making interposers for land grip arrays.

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210. Peters Michael G. ; Wang Wen-chou Vincent ; Takahashi Yasuhito ; Chou William ; Lee Michael G. ; Beilin Solomon, Reduced cross-talk noise high density signal interposer with power and ground wrap.

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211. Trezza, John, Redundant optical device array.

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212. Wang, Ge, Robust mezzanine BGA connector.

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213. Interrante, Mario J.; Sakuma, Katsuyuki, Selective area heating for 3D chip stack.

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214. Interrante, Mario J.; Sakuma, Katsuyuki, Selective area heating for 3D chip stack.

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215. Interrante, Mario J.; Sakuma, Katsuyuki, Selective area heating for 3D chip stack.

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216. Interrante, Mario J.; Sakuma, Katsuyuki, Selective area heating for 3D chip stack.

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217. Charles W. C. Lin SG, Semiconductor chip assembly with ball bond connection joint.

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218. Lin, Charles W. C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.

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219. Lin, Charles W.C.; Chiang, Cheng-Lien, Semiconductor chip assembly with bumped conductive trace.

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220. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with bumped metal pillar.

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221. Charles W. C. Lin SG, Semiconductor chip assembly with bumped molded substrate.

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222. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with bumped terminal and filler.

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223. Lin, Charles W. C.; Chen, Cheng Chung, Semiconductor chip assembly with bumped terminal, filler and insulative base.

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224. Lin,Charles W. C.; Chiang,Cheng Lien, Semiconductor chip assembly with carved bumped terminal.

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225. Wang, Chia-Chung; Lin, Charles W. C., Semiconductor chip assembly with chip in substrate cavity.

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226. Lin, Charles W. C., Semiconductor chip assembly with elongated wire ball bonded to chip and electrolessly plated to support circuit.

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227. Chiang,Cheng Lien; Lin,Charles W. C., Semiconductor chip assembly with embedded metal particle.

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228. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.

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229. Leu,Chuen Rong; Lin,Charles W. C., Semiconductor chip assembly with embedded metal pillar.

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230. Lin, Charles W. C., Semiconductor chip assembly with hardened connection joint.

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231. Lin, Charles W. C., Semiconductor chip assembly with interlocked conductive trace.

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232. Lin, Charles W.C., Semiconductor chip assembly with interlocked conductive trace.

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233. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with interlocked contact terminal.

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234. Lin,Charles W. C.; Chen,Cheng Chung; Chiang,Cheng Lien, Semiconductor chip assembly with laterally aligned bumped terminal and filler.

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235. Lin,Charles W. C.; Chen,Cheng Chung, Semiconductor chip assembly with laterally aligned filler and insulative base.

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236. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with metal containment wall and solder terminal.

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237. Wang,Chia Chung; Lin,Charles W. C., Semiconductor chip assembly with precision-formed metal pillar.

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238. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.

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239. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electrolessly plated contact terminal and connection joint.

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240. Charles W. C. Lin SG, Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.

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241. Lin, Charles W. C., Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint.

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242. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar.

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243. Lin, Charles W. C.; Chen, Cheng-Chung, Semiconductor chip assembly with welded metal pillar and enlarged plated contact terminal.

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244. Lin,Charles W. C.; Wang,Chia Chung, Semiconductor chip assembly with welded metal pillar of stacked metal balls.

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245. Lin,Charles W. C., Semiconductor chip assembly with welded metal pillar that includes enlarged ball bond.

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246. Sumikawa, Masato; Tanaka, Kazumi, Semiconductor device.

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247. Washida Tetsuro,JPX ; Ochi Katsunori,JPX, Semiconductor device with a package having a plurality of bump electrodes and module with a plurality of semiconductor.

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248. Higashida Takaaki,JPX ; Kumagai Koichi,JPX ; Matsuo Takahiro,JPX, Semiconductor element-mounting board and semiconductor device.

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249. Fujino,Takeya; Kimura,Fumihiro, Semiconductor integrated circuit and method of manufacturing the same.

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250. Haba, Belgacem, Semiconductor module with serial bus connection to multiple dies.

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251. Fritz, Donald S., Semiconductor package with stress inhibiting intermediate mounting substrate.

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252. Wang, Chuen Khiang; Suthiwongsunthorn, Nathapong; Sae Le, Kriangsak; Dimaano, Antonio Jr B; Ng, Catherine Bee Liang; Gan, Richard Te; Eng, Kian Teng, Semiconductor packages and methods of packaging semiconductor devices.

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253. Wang, Chuen Khiang; Suthiwongsunthorn, Nathapong; Sae Le, Kriangsak; Dimaano, Antonio Jr B; Ng, Catherine Bee Liang; Gan, Richard Te; Eng, Kian Teng, Semiconductor packages and methods of packaging semiconductor devices.

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254. Wang, Chuen Khiang; Suthiwongsunthorn, Nathapong; Sae Le, Kriangsak; Dimaano, Antonio Jr B; Ng, Catherine Bee Liang; Gan, Richard Te; Eng, Kian Teng, Semiconductor packages and methods of packaging semiconductor devices.

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255. Anthony,David; Anthony,Anthony; Anthony,William, Shielded energy conditioner.

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256. Gore John G., Slotted printed circuit board surface mount stress relief system.

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257. Goossen Keith-Wayne, Solder bonding of electrical components.

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258. Spielberger, Richard K.; Jensen, Ronald J.; Wagner, Thomas G., Stacked ball grid array.

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259. Buck Roy V., Stress relief substrate for solder ball grid array mounted circuits and method of packaging.

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260. Timothy W. Houtz, Stress resistant connector and method for reducing stress in housing thereof.

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261. Luvara John J. ; Quigley ; Jr. John J. ; Prasad Ray, Structure for printed circuit design.

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262. Luvara John J. ; Quigley Jay J ; Prasad Ray, Structure for printed circuit design.

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263. Canegallo, Roberto; Scandiuzzo, Mauro, Substrate assembly provided with capacitive interconnections, and manufacturing method thereof.

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264. Lin, Charles W. C., Support circuit with a tapered through-hole for a semiconductor chip assembly.

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265. Muthukumar, Sriram; Natekar, Devendra, Thin silicon based substrate.

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266. Muthukumar,Sriram; Natekar,Devendra, Thin silicon based substrate.

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267. Lin,Charles W. C.; Chiang,Cheng Lien, Three-dimensional stacked semiconductor package with metal pillar in encapsulant aperture.

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268. Faska, Tom; Dudoff, Greg, Topside active optical device apparatus and method.

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269. Anthony, Anthony A.; Anthony, William M., Universal energy conditioning interposer with circuit architecture.

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270. Anthony,Anthony A.; Anthony,William M., Universal energy conditioning interposer with circuit architecture.

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271. Anthony,Anthony A.; Anthony,William M., Universial energy conditioning interposer with circuit architecture.

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272. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B., Vertical electrical connector.

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273. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B., Vertical electrical connector.

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274. Buck, Jonathan E.; Stoner, Stuart C.; Minich, Steven E.; Johnescu, Douglas M.; Smith, Stephen B., Vertical electrical connector.

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275. Heinen, Katherine G.; Edwards, Darvin R.; Jacobs, Elizabeth G., Wafer-scale assembly of chip-size packages.

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